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  1. 20 10月, 2009 4 次提交
  3. 17 10月, 2009 1 次提交
  5. 15 10月, 2009 4 次提交
  7. 06 10月, 2009 8 次提交
    • A
      Input: fix rx51 board keymap · acf442dc
      由 Amit Kucheria 提交于 
      The original driver was written with the KEY() macro defined as (col,
row) instead of (row, col) as defined by the matrix keypad
infrastructure. So the keymap was defined accordingly. Since the
driver that was merged upstream uses the matrix keypad infrastructure,
modify the keymap accordingly.

While we are at it, fix the comments in twl4030.h and define
PERSISTENT_KEY as (r,c) instead of (c, r)

Tested on a RX51 (N900) device.
Signed-off-by: NAmit Kucheria <amit.kucheria@verdurent.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Signed-off-by: NDmitry Torokhov <dtor@mail.ru>
      acf442dc
    • R
      omap: Lock DPLL5 at boot · 7a66a39b
      由 Rajendra Nayak 提交于 
      Lock DPLL5 at 120MHz at boot. The USBHOST 120MHz f-clock and
USBTLL f-clock are the only users of this DPLL, and 120MHz is
is the only recommended rate for these clocks.

With this patch, the 60 MHz ULPI clock is generated correctly.

Tested on an OMAP3430 SDP.
Signed-off-by: NRajendra Nayak <rnayak@ti.com>
Signed-off-by: NAnand Gadiyar <gadiyar@ti.com>
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>
      7a66a39b
    • A
      OMAP3: PM: introduce a new powerdomain walk helper · ee894b18
      由 Artem Bityutskiy 提交于 
      The 'pwrdm_for_each()' function walks powerdomains with a spinlock
locked, so the the callbacks cannot do anything which may sleep.
This patch introduces a 'pwrdm_for_each_nolock()' helper which does
the same, but without the spinlock locked. This fixes the following
lockdep warning:

[    0.000000] WARNING: at kernel/lockdep.c:2460 lockdep_trace_alloc+0xac/0xec()
[    0.000000] Modules linked in:
(unwind_backtrace+0x0/0xdc) from [<c0045464>] (warn_slowpath_common+0x48/0x60)
(warn_slowpath_common+0x48/0x60) from [<c0067dd4>] (lockdep_trace_alloc+0xac/0xec)
(lockdep_trace_alloc+0xac/0xec) from [<c009da14>] (kmem_cache_alloc+0x1c/0xd0)
(kmem_cache_alloc+0x1c/0xd0) from [<c00b21d8>] (d_alloc+0x1c/0x1a4)
(d_alloc+0x1c/0x1a4) from [<c00a887c>] (__lookup_hash+0xd8/0x118)
(__lookup_hash+0xd8/0x118) from [<c00a9f20>] (lookup_one_len+0x84/0x94)
(lookup_one_len+0x84/0x94) from [<c010d12c>] (debugfs_create_file+0x8c/0x20c)
(debugfs_create_file+0x8c/0x20c) from [<c010d320>] (debugfs_create_dir+0x1c/0x20)
(debugfs_create_dir+0x1c/0x20) from [<c000e8cc>] (pwrdms_setup+0x60/0x90)
(pwrdms_setup+0x60/0x90) from [<c002e010>] (pwrdm_for_each+0x30/0x80)
(pwrdm_for_each+0x30/0x80) from [<c000e79c>] (pm_dbg_init+0x7c/0x14c)
(pm_dbg_init+0x7c/0x14c) from [<c00232b4>] (do_one_initcall+0x5c/0x1b8)
(do_one_initcall+0x5c/0x1b8) from [<c00083f8>] (kernel_init+0x90/0x10c)
(kernel_init+0x90/0x10c) from [<c00242c4>] (kernel_thread_exit+0x0/0x8)
Signed-off-by: NArtem Bityutskiy <Artem.Bityutskiy@nokia.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      ee894b18
    • K
      OMAP3: PM: Enable GPIO module-level wakeups · eb350f74
      由 Kevin Hilman 提交于 
      Currently, only GPIOs in the wakeup domain (GPIOs in bank 0) are
enabled as wakups.  This patch also enables GPIOs in the PER
powerdomain (banks 2-6) to be used as possible wakeup sources.

In addition, this patch ensures that all GPIO wakeups can wakeup
the MPU using the PM_MPUGRPSEL_<pwrdm> registers.

NOTE: this doesn't enable the individual GPIOs as wakeups, this simply
enables the per-bank wakeups at the powerdomain level.

This problem was discovered by Mike Chan when preventing the CORE
powerdomain from going into retention/off.  When CORE was allowed to
hit retention, GPIO wakeups via IO pad were working fine, but when
CORE remained on, GPIO module-level wakeups were not working properly.

To test, prevent CORE from going inactive/retention/off, thus
preventing the IO chain from being armed:

  # echo 3 > /debug/pm_debug/core_pwrdm/suspend

This ensures that GPIO wakeups happen via module-level wakeups and
not via IO pad.

Tested on 3430SDP using the touchscreen GPIO (gpio 2, in WKUP)
Tested on Zoom2 using the QUART interrup GPIO  (gpio 102, in PER)

Also, c.f. OMAP PM wiki for troubleshooting GPIO wakeup issues:
http://elinux.org/OMAP_Power_ManagementReported-by: NMike Chan <mikechan@google.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      eb350f74
    • V
      OMAP3: PM: USBHOST: clear wakeup events on both hosts · 71a80775
      由 Vikram Pandita 提交于 
      USBHOST module has 2 fclocks (for HOST1 and HOST2), only one iclock
and only a single bit in the WKST register to indicate a wakeup event.

Because of the single WKST bit, we cannot know whether a wakeup event
was on HOST1 or HOST2, so enable both fclocks before clearing the
wakeup event to ensure both hosts can properly clear the event.
Signed-off-by: NVikram Pandita <vikram.pandita@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      71a80775
    • P
      OMAP3: PM: PRCM interrupt: only handle selected PRCM interrupts · 8cb0ac99
      由 Paul Walmsley 提交于 
      Clearing wakeup sources is now only done when the PRM indicates a
wakeup source interrupt.  Since we don't handle any other types of
PRCM interrupts right now, warn if we get any other type of PRCM
interrupt.  Either code needs to be added to the PRCM interrupt
handler to react to these, or these other interrupts should be masked
off at init.

Updated after Jon Hunter's PRCM IRQ rework by Kevin Hilman.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      8cb0ac99
    • P
      OMAP3: PM: PRCM interrupt: check MPUGRPSEL register · 5d805978
      由 Paul Walmsley 提交于 
      PM_WKST register contents should be ANDed with the contents of the
MPUGRPSEL registers.  Otherwise the MPU PRCM interrupt handler could
wind up clearing wakeup events meant for the IVA PRCM interrupt
handler. A future revision to this code should be to read a cached
version of MPUGRPSEL from the powerdomain code, since PRM reads are
relatively slow.

Updated after Jon Hunter's PRCM IRQ change by Kevin Hilman
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      5d805978
    • J
      OMAP3: PM: Prevent hang in prcm_interrupt_handler · 77da2d91
      由 Jon Hunter 提交于 
      There are two scenarios where a race condition could result in a hang
in the prcm_interrupt handler. These are:

1). Waiting for PRM_IRQSTATUS_MPU register to clear.
Bit 0 of the PRM_IRQSTATUS_MPU register indicates that a wake-up event
is pending for the MPU. This bit can only be cleared if the all the
wake-up events latched in the various PM_WKST_x registers have been
cleared. If a wake-up event occurred during the processing of the prcm
interrupt handler, after the corresponding PM_WKST_x register was
checked but before the PRM_IRQSTATUS_MPU was cleared, then the CPU
would be stuck forever waiting for bit 0 in PRM_IRQSTATUS_MPU to be
cleared.

2). Waiting for the PM_WKST_x register to clear.
Some power domains have more than one wake-up source. The PM_WKST_x
registers indicate the source of a wake-up event and need to be cleared
after a wake-up event occurs. When the PM_WKST_x registers are read and
before they are cleared, it is possible that another wake-up event
could occur causing another bit to be set in one of the PM_WKST_x
registers. If this did occur after reading a PM_WKST_x register then
the CPU would miss this event and get stuck forever in a loop waiting
for that PM_WKST_x register to clear.

This patch address the above race conditions that would result in a
hang.
Signed-off-by: NJon Hunter <jon-hunter@ti.com>
Reviewed-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
      77da2d91
  9. 29 9月, 2009 1 次提交
  11. 25 9月, 2009 8 次提交
  13. 23 9月, 2009 7 次提交
  15. 20 9月, 2009 2 次提交
  17. 17 9月, 2009 1 次提交
  19. 04 9月, 2009 4 次提交
    • P
      OMAP: omap_hwmod: call omap_hwmod init at boot; create interconnects · 02bfc030
      由 Paul Walmsley 提交于 
      Connect the omap_hwmod code to the kernel boot.  Create some basic
interconnect and device structures for OMAP2/3 chips.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      02bfc030
    • P
      OMAP2/3/4: create omap_hwmod layer · 63c85238
      由 Paul Walmsley 提交于 
      OMAP SoCs can be considered a collection of hardware IP blocks
connected by various interconnects.  The bus topology and device
integration data is somewhat more complex than platform_device can
encode.  This patch creates code and structures to manage information
about OMAP on-chip devices ("hardware modules") and their integration
to the rest of the chip.  Hardware module data is intended to be
generated dynamically from the TI hardware database for the OMAP4
chips and beyond, easing Linux support for new chip variants.

This code currently:

- resets and configures all hardware modules upon startup, reducing bootloader
  dependencies;

- provides hooks for Linux driver model code to enable, idle, and shutdown
  hardware modules (forthcoming patch);

- waits for hardware modules to leave idle once their clocks
  are enabled and OCP_SYSCONFIG bits are set appropriately.

- provides a means to pass arbitrary IP block configuration data (e.g.,
  FIFO size) to the device driver (via the dev_attr void pointer)

In the future this code is intended to:

- estimate interconnect bandwidth and latency characteristics to
  ensure constraints are satisfied during DVFS

- provide *GRPSEL bit data to the powerdomain code

- handle pin/ball muxing for devices

- generate IO mapping information dynamically

- supply device firewall configuration data

- provide hardware module data to other on-chip coprocessor software

- allow the removal of the "disable unused clocks" code in the OMAP2/3
  clock code

This patch represents a collaborative effort involving many people from TI,
Nokia, and the Linux-OMAP community.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Vikram Pandita <vikram.pandita@ti.com>
Cc: Sakari Poussa <sakari.poussa@nokia.com>
Cc: Anand Sawant <sawant@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Eric Thomas <ethomas@ti.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
      63c85238
    • P
      OMAP2/3 board-*.c files: read bootloader configuration earlier · b3c6df3a
      由 Paul Walmsley 提交于 
      Most board-*.c files read configuration data from the bootloader in
their .init_machine() function.  This needs to happen earlier, at some
point before omap2_init_common_hw() is called.  This is because a
future patch will use the bootloader serial console port information
to enable the UART clocks earlier, immediately after omap2_clk_init().
This is in turn necessary since otherwise clock tree usecounts on
clocks like dpll4_m2x2_ck will be bogus, which can cause the
currently-active console UART clock to be disabled during boot.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      b3c6df3a
    • P
      OMAP2/3/4 PRCM: add module IDLEST wait code · 71348bca
      由 Paul Walmsley 提交于 
      After a hardware module's clocks are enabled, Linux must wait for it
to indicate readiness via its IDLEST bit before attempting to access
the device, otherwise register accesses to the device may trigger an
abort.  This has traditionally been implemented in the clock
framework, but this is the wrong place for it: the clock framework
doesn't know which module clocks must be enabled for a module to leave
idle; and if a module is not in smart-idle mode, it may never leave
idle at all.  This type of information is best stored in a
per-hardware module data structure (coming in a following patch),
rather than a per-clock data structure.  The new code will use these new
functions to handle waiting for modules to enable.

Once hardware module data is filled in for all of the on-chip devices,
the clock framework code to handle IDLEST waiting can be removed.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
      71348bca