Plug the partitioning layer into the GICv3 PPI code, parsing the
DT and building the partition affinities and providing the generic
code with partition data and callbacks.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-5-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

We've unfortunately started seeing a situation where percpu interrupts
are partitioned in the system: one arbitrary set of CPUs has an
interrupt connected to a type of device, while another disjoint
set of CPUs has the same interrupt connected to another type of device.

This makes it impossible to have a device driver requesting this interrupt
using the current percpu-interrupt abstraction, as the same interrupt number
is now potentially claimed by at least two drivers, and we forbid interrupt
sharing on per-cpu interrupt.

A solution to this is to turn things upside down. Let's assume that our
system describes all the possible partitions for a given interrupt, and
give each of them a unique identifier. It is then possible to create
a namespace where the affinity identifier itself is a form of interrupt
number. At this point, it becomes easy to implement a set of partitions
as a cascaded irqchip, each affinity identifier being the HW irq.

This allows us to keep a number of nice properties:
- Each partition results in a separate percpu-interrupt (with a restrictied
  affinity), which keeps drivers happy.
- Because the underlying interrupt is still per-cpu, the overhead of
  the indirection can be kept pretty minimal.
- The core code can ignore most of that crap.

For that purpose, we implement a small library that deals with some of
the boilerplate code, relying on platform-specific drivers to provide
a description of the affinity sets and a set of callbacks.
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Link: http://lkml.kernel.org/r/1460365075-7316-4-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Commit 2a078705 ("irqchip/mips-gic: Use gic_vpes instead of
NR_CPUS") & commit 78930f09 ("irqchip/mips-gic: Clear percpu_masks
correctly when mapping") both introduce code which accesses gic_vpes
entries in the pcpu_masks array. However, this array has length NR_CPUS.
If NR_CPUS is less than gic_vpes (ie. the kernel supports use of less
CPUs than are present in the system) then we overrun the array, clobber
some other data & generally die pretty promptly.

Most notably this affects uniprocessor kernels running on any multicore
or multithreaded Malta with a GIC (ie. the vast majority of real Malta
boards).

Fix this by only accessing up to min(gic_vpes, NR_CPUS) entries in the
pcpu_masks array, preventing the array overrun.

Fixes: 2a078705 ("irqchip/mips-gic: Use gic_vpes instead of NR_CPUS")
Fixes: 78930f09 ("irqchip/mips-gic: Clear percpu_masks correctly when mapping")
Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Link: http://lkml.kernel.org/r/1461234714-9975-1-git-send-email-paul.burton@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This config is selected by CONFIG_ARCH_HISI, so there is no point to have it
user configurable.

While at it move the config option to the proper place in the alphabetically
sorted option list.
Requested-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NMa Jun <majun258@huawei.com>
Cc: mark.rutland@arm.com
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: Catalin.Marinas@arm.com
Cc: guohanjun@huawei.com
Cc: Will.Deacon@arm.com
Cc: huxinwei@huawei.com
Cc: lizefan@huawei.com
Cc: dingtianhong@huawei.com
Cc: zhaojunhua@hisilicon.com
Cc: liguozhu@hisilicon.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1458723993-21044-3-git-send-email-majun258@huawei.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Each mbigen device is represented as a independent platform device. If the
devices belong to the same mbigen hardware module, then the register space for
these devices is the same. That leads to a resource conflict.

The solution for this is to represent the mbigen module as a platform device
and make the mbigen devices subdevices of that. The register space is
associated to the mbigen module and therefor the resource conflict is avoided.

[ tglx: Massaged changelog, cleaned up the code and removed the silly printk ]
Signed-off-by: NMa Jun <majun258@huawei.com>
Cc: mark.rutland@arm.com
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: Catalin.Marinas@arm.com
Cc: guohanjun@huawei.com
Cc: Will.Deacon@arm.com
Cc: huxinwei@huawei.com
Cc: lizefan@huawei.com
Cc: dingtianhong@huawei.com
Cc: zhaojunhua@hisilicon.com
Cc: liguozhu@hisilicon.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1458203641-17172-3-git-send-email-majun258@huawei.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Current code calls irq_domain_alloc_irqs_parent() in .alloc,
so it should call irq_domain_free_irqs_parent() accordingly in .free.
Fix it by switching to use irq_domain_free_irqs_common() instead of
the open-coded private implementation.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Link: http://lkml.kernel.org/r/1458477845.28679.1.camel@ingics.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The "msi_domain" variable is NULL here so it leads to a NULL dereference.  It
looks like we actually intended to free "middle_domain".

Fixes: e6b78f2c ('irqchip: Add the Alpine MSIX interrupt controller')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: kernel-janitors@vger.kernel.org
Cc: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Link: http://lkml.kernel.org/r/20160311081442.GE31887@mwandaSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The of_io_request_and_map() returns a valid pointer in iomem region or
ERR_PTR(), check for NULL always fails and may cause a NULL pointer
dereference on error path.

Fixes: 25e34b44 ("irqchip/mxs: Prepare driver for hardware with different offsets")
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Oleksij Rempel <linux@rempel-privat.de>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1457486500-10237-1-git-send-email-vz@mleia.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The of_io_request_and_map() returns a valid pointer in iomem region or
ERR_PTR(), check for NULL always fails and may cause a NULL pointer
dereference on error path.

Fixes: 0e841b04 ("irqchip/sunxi-nmi: Switch to of_io_request_and_map() from of_iomap()")
Signed-off-by: NVladimir Zapolskiy <vz@mleia.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1457486489-10189-1-git-send-email-vz@mleia.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

In the add-on file for the GIC dealing with the RealView family
we currently only handle the PB11MPCore, let's extend this to
manage the RealView EB ARM11MPCore as well. The Revision B of the
ARM11MPCore core tile is a bit special and needs special handling
as it moves a system control register around at random.

Cc: Arnd Bergmann <arnd@arndb.de>
Cc: devicetree@vger.kernel.org
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This patch adds the Alpine MSIX interrupt controller driver.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: NTsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Always return IRQ_SET_MASK_OK_DONE instead of IRQ_SET_MASK_OK when the
affinity has been updated. When using stacked irqchips, returning
IRQ_SET_MASK_OK_DONE means skipping all descendant irqchips.
Signed-off-by: NAntoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

gicv3_init_bases() is the only caller for its_init(),
also it is a __init function, so mark its_init() as __init too,
then recursively mark the functions called as __init.

This will help to introduce ITS initialization using ACPI tables as
we will use acpi_table_parse_entries family functions there which
belong to __init section as well.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NTomasz Nowicki <tn@semihalf.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The gic_root_node variable defined in ITS driver is not actually
used, so just remove it.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Following ACPI spec:
On systems supporting GICv3 and above, GICR Base Address in MADT GICC
structure holds the 64-bit physical address of the associated Redistributor.
If all of the GIC Redistributors are in the always-on power domain,
GICR structures should be used to describe the Redistributors instead,
and this field must be set to 0.

It means that we have two ways to initialize registirbutors map.
1. via GICD structure which can accommodate many redistributors as a region
2. via GICC which is able to describe single redistributor

This patch is going to add support for second option.
Considering redistributors, GICD and GICC subtables have be mutually
exclusive. While discovering and mapping redistributor, we need to know
its size in advance. For the GICC case, redistributor can be in
a power-domain that is off, thus we cannot relay on GICR TYPER register.
Therefore, we get GIC version from distributor register and map 2xSZ_64K
for GICv3 and 4xSZ_64K for GICv4.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NTomasz Nowicki <tn@semihalf.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

With the refator of gic_of_init(), GICv3/4 can be initialized
by gic_init_bases() with gic distributor base address and gic
redistributor region(s).

So get the redistributor region base addresses from MADT GIC
redistributor subtable, and the distributor base address from
GICD subtable to init GICv3 irqchip in ACPI way.

Note: GIC redistributor base address may also be provided in
GICC structures on systems supporting GICv3 and above if the GIC
Redistributors are not in the always-on power domain, this
patch didn't implement such feature yet.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NTomasz Nowicki <tn@semihalf.com>
Signed-off-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Isolate hardware abstraction (FDT) code to gic_of_init().
Rest of the logic goes to gic_init_bases() and expects well
defined data to initialize GIC properly. The same solution
is used for GICv2 driver.

This is needed for ACPI initialization later.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NTomasz Nowicki <tomasz.nowicki@linaro.org>
Signed-off-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

The new property will allow to specify the range of GIC hwirqs to use for IPIs.

This is an optinal property. We preserve the previous behaviour of allocating
the last 2 * gic_vpes if it's not specified or DT is not supported.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRob Herring <robh@kernel.org>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-20-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This commit does several things to avoid breaking bisectability.

	1- Remove IPI init code from irqchip/mips-gic
	2- Implement the new irqchip->send_ipi() in irqchip/mips-gic
	3- Select GENERIC_IRQ_IPI Kconfig symbol for MIPS_GIC
	4- Change MIPS SMP to use the generic IPI implementation

Only the SMP variants that use GIC were converted as it's the only irqchip that
will have the support for generic IPI for now.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-18-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

When setting the mapping for a hwirq, make sure we clear percpu_masks for
all other cpus in case it was set previously.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-16-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

NR_CPUS is set by Kconfig and could be much higher than what actually is in the
system.

gic_vpes should be a true representitives of the number of cpus in the system,
so use it instead.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-15-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Now the root gic_irq_domain is split into device and IPI domains.

This form provides a better representation of how the root domain is split into
2. One for devices and one for IPIs.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-14-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Add a new ipi domain on top of the normal domain.

MIPS GIC now supports dynamic allocation of an IPI.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-13-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Moving an SPI around doesn't require any extra work from the rest
of the stack, and specially not for MSI-generated SPIs.

It is then worth returning IRQ_SET_MASK_OK_DONE instead of
IRQ_SET_MASK_OK, and simplify the other irqchips that rely on
this behaviour (GICv2m and Marvell's ODMI controller).
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1455894029-17270-1-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commits adds a new irqchip driver that handles the ODMI
controller found on Marvell 7K/8K processors. The ODMI controller
provide MSI interrupt functionality to on-board peripherals, much like
the GIC-v2m.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

ts4800_ic_ops is only referenced in this driver, so make it static.
In additional, it's never get modified thus also make it const.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Reviewed-by: NDamien Riegel <damien.riegel@savoirfairelinux.com>
Link: https://lkml.kernel.org/r/1455457804.13175.1.camel@ingics.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The writel() immediately after this has a barrier, anyway.
Signed-off-by: NEric Anholt <eric@anholt.net>
Link: https://lkml.kernel.org/r/1454620468-31303-1-git-send-email-eric@anholt.netSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Technologic Systems TS-4800 is an i.MX515 board, so its drivers
are useless unless building a SOC_IMX51 kernel, except for build
testing purposes.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Damien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/20160209111920.1ec318bd@endymionSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This adds support for the secondary interrupt controller used in Sigma
Designs SMP86xx and SMP87xx chips.
Signed-off-by: NMans Rullgard <mans@mansr.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453313237-18570-2-git-send-email-mans@mansr.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The rework of the driver missed to move the call to set_handle_irq() into
asm9260_of_init(). As a consequence no interrupt entry point is installed and
no interrupts are delivered

Solution is:
Install the interrupt entry handler.

Fixes: 7e4ac676 ("irqchip/mxs: Add Alphascale ASM9260 support")
Signed-off-by: NOleksij Rempel <linux@rempel-privat.de>
Link: https://lkml.kernel.org/r/1454061473-24957-1-git-send-email-linux@rempel-privat.deSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Function its_alloc_tables() maintains two local variables, "order" and
and "alloc_size", to hold memory size that has been allocated to
ITS_BASEn. We don't always refresh the variable alloc_size whenever
value of the variable order changes, causing the following two
problems.

  - Cache flush operation with size more than required.
  - Information reported by pr_info is not correct.

Use a helper macro that converts page order to size in bytes instead of
variable "alloc_size" to fix both the problems.
Signed-off-by: NShanker Donthineni <shankerd@codeaurora.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453553867-27003-2-git-send-email-albeu@free.frSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The driver stays the same but the initialization changes a bit.
For OF boards we now get the memory map from the OF node and use
a linear mapping instead of the legacy mapping. For legacy boards
we still use a legacy mapping and just pass down all the parameters
from the board init code.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.frSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The irq-armada-370-xp driver can only be built for ARM 32 bits. The mvebu
family had grown with a new ARM64 SoC which will also select the
ARCH_MEVBU configuration. Since "ARM: mvebu: use the ARMADA_370_XP_IRQ
option", the ARM32 mvebu SoC directly select this new option. Selecting
it by default when ARCH_MEVBU is selected is no more needed.

This patch removes this dependency, thanks to this, a kernel for ARM64
mvebu SoC can be built without error due this driver.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1454951660-13289-3-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Add support for allocating multiple MSIs at the same time, so that the
MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info
structure.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-6-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In order to make the output of /proc/interrupts, use shorter names for
the irq_chip registered by the irq-armada-370-xp driver. Using capital
letters also matches better what is done for the GIC driver, which
uses just "GIC" as the irq_chip->name.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

As suggested by Gregory Clement, this commit adjusts the
irq-armada-370-xp driver to use the PCI_MSI_DOORBELL_START define in
the armada_370_xp_handle_msi_irq() function, rather than hardcoding
its value.
Suggested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commit moves the irq-armada-370-xp driver from using the
PCI-specific MSI infrastructure to the generic MSI infrastructure, to
which drivers are progressively converted.

In this hardware, the MSI controller is directly bundled inside the
interrupt controller, so we have a single Device Tree node to which
multiple IRQ domaines are attached: the wired interrupt domain and the
MSI interrupt domain. In order to ensure that they can be
differentiated, we have to force the bus_token of the wired interrupt
domain to be DOMAIN_BUS_WIRED. The MSI domain bus_token is
automatically set to the appropriate value by
pci_msi_create_irq_domain().
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Suggested-by: NMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1455115621-22846-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Instead of building the irq-armada-370-xp driver directly when
CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate
CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option.

This allows this option to select other interrupt-related Kconfig
options (which will be needed in follow-up commits) rather than having
such selects done from arch/arm/mach-<foo>/.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

When the GIC is using EOImode==1, the EOI is done immediately,
leaving the deactivation to be performed when the EOI was
previously done.

Unfortunately, the ITS is not aware of the EOImode at all, and
blindly EOIs the interrupt again. On most systems, this is ignored
(despite being a programming error), but some others do raise a
SError exception as there is no priority drop to perform for this
interrupt.

The fix is to stop trying to be clever, and always call into the
underlying GIC to perform the right access, irrespective of the
more we're in.

[Marc: Reworked commit message]

Fixes: 0b996fd3 ("irqchip/GICv3: Convert to EOImode == 1")
Cc: stable@vger.kernel.org
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NAshok Kumar <ashoks@broadcom.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>