For RK3399's GRF module, if we want to operate the graphic related grf
registers, we need to enable the pclk_vio_grf which supply power for VIO
GRF IOs, so it's better to introduce an optional grf clock in driver.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Reviewed-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NTomasz Figa <tomasz.figa@chromium.com>

The hardware IC designed that VOP must output the RGB10 video format to
eDP contoller, and if eDP panel only support RGB8, then eDP contoller
should cut down the video data, not via VOP contoller, that's why we need
to hardcode the VOP output mode to RGA10 here.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Acked-by: NMark Yao <mark.yao@rock-chips.com>
Reviewed-by: NTomasz Figa <tomasz.figa@chromium.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>

Rockchip VOP couldn't output YUV video format for eDP controller, so
when driver detect connector support YUV video format, we need to hack
it down to RGB888.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Acked-by: NMark Yao <mark.yao@rock-chips.com>
Reviewed-by: NTomasz Figa <tomasz.figa@chromium.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>

Some boards don't need to declare a panel device node, like the
display interface is DP monitors, so it's necessary to make the
panel detect to an optional action.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Acked-by: NMark Yao <mark.yao@rock-chips.com>
Reviewed-by: NTomasz Figa <tomasz.figa@chromium.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>

RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Acked-by: NMark Yao <mark.yao@rock-chips.com>
Reviewed-by: NTomasz Figa <tomasz.figa@chromium.com>
Reviewed-by: NSean Paul <seanpaul@chromium.org>

eDP controller need to declare which vop provide the video source,
and it's defined in GRF registers.

But different chips have different GRF register address, so we need to
create a device data to declare the GRF messages for each chips.
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Acked-by: NMark Yao <mark.yao@rock-chips.com>
Reviewed-by: NTomasz Figa <tfiga@chromium.org>
Reviewed-by: NSean Paul <seanpaul@chromium.org>

The DP needs to have resumed once the DRM driver calls
drm_atomic_helper_resume, otherwise the DP clock is still disabled when
the DRM core enables the DP bridge.

Would be nice to use device_pm_wait_for_dev to synchronize these
devices, but the DRM device doesn't know what specific implementation
this bridge has.
Signed-off-by: NTomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Caesar Wang <wxt@rock-chips.com>
Cc: Douglas Anderson <dianders@chromium.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
Link: http://patchwork.freedesktop.org/patch/msgid/1465224813-7359-2-git-send-email-tomeu.vizoso@collabora.com

We need to take care of the vop status when use
rockchip_drm_crtc_mode_config, if vop is disabled,
the function would failed, that is terrible.

Save output_type and output_mode into rockchip_crtc_state,
it's nice to make them into atomic.
Signed-off-by: NMark Yao <mark.yao@rock-chips.com>
Tested-by: NJohn Keeping <john@metanate.com>

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Acked-by: NMark Yao <mark.yao@rock-chips.com>
Tested-by: NCaesar Wang <wxt@rock-chips.com>
Tested-by: NDouglas Anderson <dianders@chromium.org>
Tested-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NYakir Yang <ykk@rock-chips.com>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>