Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

setup_early_printk() can be static, and with that, we can kill off
the early initialization variable and move the CON_BOOT check in
to the function body.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This conditionalizes gUSA support. gUSA is not supported on
SMP configurations, and it's not necessary there anyways due
to having other atomicity options (ie, movli.l/movco.l).

Anything implementing the LL/SC semantics (all SH-4A CPUs)
can switch to userspace atomicity implementations without
requiring gUSA. This is left default-enabled on all UP so
that glibc doesn't break.

Those that know what they are doing can disable this explicitly.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Currently gUSA toggles hardirqs to disable preemption in the signal
handler. Make the preemption toggling explicit, and kill off some
CONFIG_PREEMPT ifdefs in the process.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements a fast-path for small (less than 12 bytes) copies,
with the existing path treated as the slow-path and left as the default
behaviour for all other copy sizes.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Currently clock propagation only works for one level, but we have some
clocks which need to propagate multiple levels, so make this recursive.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Not all of the SH-X2 URAM blocks are mapped in the same place,
SH7785 happens to map it on the opposite end of the address space
from SH7722, correct the addresses.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This moves off of smp_processor_id() and only sets the probe
information for the boot CPU directly. This will be copied out
for the secondaries, so there's no reason to do this each time.

This also allows for some header tidying.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

When using URAM in NUMA mode another active region is needed.
Bump this up so we don't trigger the region truncation in
add_active_range().
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There was some debug code left in here that caused the pin changes
to never be hit. Kill that off, and all is well.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

We already set this in arch/sh/mm/Kconfig, don't set a conflicting
one in arch/sh/Kconfig too..
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

4kB pages are unstable on extended mode TLB, it's recommended
that TLB compat mode be used when using a 4kB PAGE_SIZE. Set
the default for extended mode to 8kB.

This should have negligible impact, as other than the extra swap
cache entry bits, there's no reason to use the extended mode TLB
with 4kB pages.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The probing logic works for both URAM and L2, with no way to
distinguish between the two. Disable the probing for now and
let the CPU subtypes that have this in a real L2 configuration
explicitly say so.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The uClinux MTD device uses _ebss, add the symbol and corresponding
export.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

These were right the first time. Either a thinko or
building in the wrong tree. Revert this.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Calculate the number of cache aliases on probed L2 caches, and while
we're at it, print out the detected statistics at boot time for these
also.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

We stopped referencing these functions unconditionally when the
old entry.S code was refactored, so this is just dead code at
present. Kill it off.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There was an off-by-1 on the cache alias detection logic on SH-4,
which caused n_aliases to always be 1 even when the page size
precluded the existence of aliases.

With this corrected, 64KB pages happily reports n_aliases == 0, and
hits the appropriate fast paths in the flushing routines.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds basic support for SH-X3 SMP (4 CPUs).

More IPI and cache debugging is necessary, mostly interfacing the
d-cache coherency and the I-cache broadcast invalidates. Only for
testing at present!
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Now that the SMP stubs are in place, call in to the setup code
to be defined by the platform.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

There was a very preliminary bunch of SMP code scattered around for the
SH7604 microcontrollers from way back when, and it has mostly suffered
bitrot since then. With the tree already having been slowly getting
prepped for SMP, this plugs in most of the remaining platform-independent
bits.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This implements initial support for the SMP INTC (particularly
INTC2) controllers.

These are largely implemented as conventional blocks, with
register sets grouped together at fixed strides relative to
the CPU id.
Signed-off-by: NMagnus Damm <damm@igel.co.jp>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This adds the TLB flushing routines for SMP systems, based on
the MIPS implementation, with some additional SH-specific
flush routines.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

current_cpu_data uses smp_processor_id() in order to find the
corresponding cpu_data. As the cache descs are all currently
identical, just have this look at probed results from the boot
CPU.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This consolidates the cpu_data definitions and gets rid of the special
boot_cpu_data. It's made a wrapper to the boot CPU, in order to keep
the existing in-tree users happy.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The cpufreq driver banner is currently printed for each CPU, move
it down so it's not as noisy and it's only printed once.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The Maple bus is SEGA's proprietary serial bus for peripherals
(keyboard, mouse, controller etc). The bus is capable of some
(limited) hotplugging and operates at up to 2 M/bits.

Drivers of one sort or another existed/exist for 2.4 and a rudimentary
port, which didn't support the 2.6 device driver model was also in
existence.

This driver - for the bus logic itself and for the keyboard (other
drivers will follow) are based on the code and concepts of those old
drivers but have lots of completely rewritten parts.

I have the maple bus code as a built in now as that seems the sane and
rational way to handle something like that - you either want the bus
or you don't.
Signed-off-by: NAdrian McMenamin <adrian@mcmen.demon.co.uk>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This update moves the flash mapping for the Magic Panel into the board
setup. It also removes references to the old MTD mapping option in the
defconfig.

Signed-off by: Markus Brunner <super.firetwister@gmail.com>
Signed-off by: Mark Jonas <toertel@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Support CF IDE on R2D-1 boards.
Signed-off-by: NAoi Shinkai <shinkoi2005@gmail.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

The extended mode TLB requires both 64-bit PTEs and a 64-bit pgprot,
correspondingly, the PGD also has to be 64-bits, so fix that up.

The kernel and user permission bits really are decoupled in early
cuts of the silicon, which means that we also have to set corresponding
kernel permissions on user pages or we end up with user pages that the
kernel simply can't touch (!).

Finally, with those things corrected, really enable MMUCR.ME and
correct the PTEA value (this simply needs to be the upper 32-bits
of the PTE, with the size and protection bit encoding).
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Add SH7785 URAM as node 1, follows the SH-X3 change.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

This fixes up the port calculation logic for non-SuperIO accesses,
before these were always matching the MRSHPC base, now just make
sure the original port is handed back if it's not in the I/O port
range.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Trivial build fix.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

Get the IRL->IRQ stuff building.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>