- 29 5月, 2012 7 次提交
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由 Mauro Carvalho Chehab 提交于
Remove some information that it is duplicated at the MCE log, and don't have much usage for the error. Those data will be added again, when creating a trace function that outputs both memory errors and MCE fields. Cc: Aristeu Rozanski <arozansk@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Now that all drivers got converted to use the new ABI, we can drop the old one. Acked-by: NChris Metcalf <cmetcalf@tilera.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
The legacy edac ABI is going to be removed. Port the driver to use and benefit from the new API functionality. Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
The number of pages is a dimm property. Move it to the dimm struct. After this change, it is possible to add sysfs nodes for the DIMM's that will properly represent the DIMM stick properties, including its size. A TODO fix here is to properly represent dual-rank/quad-rank DIMMs when the memory controller represents the memory via chip select rows. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Acked-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Almost all edac drivers initialize csrow_info->first_page, csrow_info->last_page and csrow_info->page_mask. Those vars are used inside the EDAC core, in order to calculate the csrow affected by an error, by using the routine edac_mc_find_csrow_by_page(). However, very few drivers actually use it: e752x_edac.c e7xxx_edac.c i3000_edac.c i82443bxgx_edac.c i82860_edac.c i82875p_edac.c i82975x_edac.c r82600_edac.c There also a few other drivers that have their own calculus formula internally using those vars. All the others are just wasting time by initializing those data. While initializing data without using them won't cause any troubles, as those information is stored at the wrong place (at csrows structure), it is better to remove what is unused, in order to simplify the next patch. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Acked-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Jiri Kosina <jkosina@suse.cz> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
On systems based on chip select rows, all channels need to use memories with the same properties, otherwise the memories on channels A and B won't be recognized. However, such assumption is not true for all types of memory controllers. Controllers for FB-DIMM's don't have such requirements. Also, modern Intel controllers seem to be capable of handling such differences. So, we need to get rid of storing the DIMM information into a per-csrow data, storing it, instead at the right place. The first step is to move grain, mtype, dtype and edac_mode to the per-dimm struct. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Reviewed-by: NBorislav Petkov <borislav.petkov@amd.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Borislav Petkov <borislav.petkov@amd.com> Cc: Mark Gross <mark.gross@intel.com> Cc: Jason Uhlenkott <juhlenko@akamai.com> Cc: Tim Small <tim@buttersideup.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: Olof Johansson <olof@lixom.net> Cc: Egor Martovetsky <egor@pasemi.com> Cc: Michal Marek <mmarek@suse.cz> Cc: Jiri Kosina <jkosina@suse.cz> Cc: Joe Perches <joe@perches.com> Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Hitoshi Mitake <h.mitake@gmail.com> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: James Bottomley <James.Bottomley@parallels.com> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Cc: Shaohui Xie <Shaohui.Xie@freescale.com> Cc: Josh Boyer <jwboyer@gmail.com> Cc: Mike Williams <mike@mikebwilliams.com> Cc: linuxppc-dev@lists.ozlabs.org Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
The way a DIMM is currently represented implies that they're linked into a per-csrow struct. However, some drivers don't see csrows, as they're ridden behind some chip like the AMB's on FBDIMM's, for example. This forced drivers to fake^Wvirtualize a csrow struct, and to create a mess under csrow/channel original's concept. Move the DIMM labels into a per-DIMM struct, and add there the real location of the socket, in terms of csrow/channel. Latter patches will modify the location to properly represent the memory architecture. All other drivers will use a per-csrow type of location. Some of those drivers will require a latter conversion, as they also fake the csrows internally. TODO: While this patch doesn't change the existing behavior, on csrows-based memory controllers, a csrow/channel pair points to a memory rank. There's a known bug at the EDAC core that allows having different labels for the same DIMM, if it has more than one rank. A latter patch is need to merge the several ranks for a DIMM into the same dimm_info struct, in order to avoid having different labels for the same DIMM. The edac_mc_alloc() will now contain a per-dimm initialization loop that will be changed by latter patches in order to match other types of memory architectures. Reviewed-by: NAristeu Rozanski <arozansk@redhat.com> Reviewed-by: NBorislav Petkov <borislav.petkov@amd.com> Cc: Doug Thompson <norsk5@yahoo.com> Cc: Ranganathan Desikan <ravi@jetztechnologies.com> Cc: "Arvind R." <arvino55@gmail.com> Cc: "Niklas Söderlund" <niklas.soderlund@ericsson.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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- 22 3月, 2012 3 次提交
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由 Hui Wang 提交于
>From the driver design, the variable limit wants to compare with its previous value, we should set the value of limit instead of the value of tmp_mb to the variable prev. Signed-off-by: NHui Wang <jason77.wang@gmail.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Hui Wang 提交于
We can identify dram interleave mode from the Dram Rule register rather than Dram Interleave list register. In this context, the reg of INTERLEAVE_MODE(reg) contains the Dram Interleave list register, we can't get interleave mode from the reg, while the variable interleave_mode saves the the mode got from the Dram Rule register, so we use the variable to replace INTERLEAVE_MDDE(reg) here. Signed-off-by: NHui Wang <jason77.wang@gmail.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
As reported by Josh Boyer <jwboyer@redhat.com>: > drivers/edac/sb_edac.c: In function 'get_memory_error_data': > drivers/edac/sb_edac.c:861:2: warning: left shift count >= width of type > [enabled by default] > <snip> > ERROR: "__udivdi3" [drivers/edac/sb_edac.ko] undefined! > make[1]: *** [__modpost] Error 1 > make: *** [modules] Error 2 PS.: compile-tested only Reported-by: NJosh Boyer <jwboyer@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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- 19 3月, 2012 1 次提交
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由 Lionel Debroux 提交于
These const tables are currently marked __devinitdata, but Documentation/PCI/pci.txt says: "o The ID table array should be marked __devinitconst; this is done automatically if the table is declared with DEFINE_PCI_DEVICE_TABLE()." So use DEFINE_PCI_DEVICE_TABLE(x). Based on PaX and earlier work by Andi Kleen. Signed-off-by: NLionel Debroux <lionel_debroux@yahoo.fr> Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 21 12月, 2011 1 次提交
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由 Kevin Winchester 提交于
Several fields in struct cpuinfo_x86 were not defined for the !SMP case, likely to save space. However, those fields still have some meaning for UP, and keeping them allows some #ifdef removal from other files. The additional size of the UP kernel from this change is not significant enough to worry about keeping up the distinction: text data bss dec hex filename 4737168 506459 972040 6215667 5ed7f3 vmlinux.o.before 4737444 506459 972040 6215943 5ed907 vmlinux.o.after for a difference of 276 bytes for an example UP config. If someone wants those 276 bytes back badly then it should be implemented in a cleaner way. Signed-off-by: NKevin Winchester <kjwinchester@gmail.com> Cc: Steffen Persvold <sp@numascale.com> Link: http://lkml.kernel.org/r/1324428742-12498-1-git-send-email-kjwinchester@gmail.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
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- 14 12月, 2011 1 次提交
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由 Borislav Petkov 提交于
No functionality change, this is done so that in a follow-on patch all queued-up MCEs can be decoded after registering on the chain. Signed-off-by: NBorislav Petkov <borislav.petkov@amd.com>
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- 01 11月, 2011 3 次提交
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由 Mark A. Grondona 提交于
The edac driver for Sandy Bridge was found to be reporting "FPM" for edac_mode, which clearly doesn't make sense. It was found that sb_edac.c:get_dimm_config was reusing a variable for both mem_type and edac_type, and thus was overwriting the value after setting it correctly. This patch fixes that issue. Before the patch: /sys/devices/system/edac/mc/mc0/csrow0/edac_mode:FPM /sys/devices/system/edac/mc/mc0/csrow1/edac_mode:FPM /sys/devices/system/edac/mc/mc0/csrow2/edac_mode:FPM /sys/devices/system/edac/mc/mc0/csrow3/edac_mode:FPM After: /sys/devices/system/edac/mc/mc0/csrow0/edac_mode:S4ECD4ED /sys/devices/system/edac/mc/mc0/csrow1/edac_mode:S4ECD4ED /sys/devices/system/edac/mc/mc0/csrow2/edac_mode:S4ECD4ED /sys/devices/system/edac/mc/mc0/csrow3/edac_mode:S4ECD4ED Signed-off-by: NMark A. Grondona <mgrondona@llnl.gov> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
Some changes on it were required due to changeset cd90cc84c6bf0, that changed the glue with the MCE logic. Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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由 Mauro Carvalho Chehab 提交于
This driver is known to work on mine and Tony's test environments, using software error injection, and a partial hardware/software error injection tool. There's no broader range test yet to double check if the error decoding logic will actually point to the right DIMM, so use it with care. More tests are required to be sure that the driver will work on all different types of memory configurations. If you're willing to risk using it, I suggest you to enable EDAC debugs for your test machines, as the debug logs helps to track what's going inside the driver. Please feed me with bug reports, if you notice that the driver is miss-behaving. Tested-by: NTony Luck <tony.luck@intel.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@redhat.com>
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