1. 26 7月, 2016 1 次提交
  2. 12 5月, 2016 1 次提交
  3. 20 4月, 2016 1 次提交
  4. 16 4月, 2016 1 次提交
  5. 12 4月, 2016 2 次提交
  6. 09 3月, 2016 3 次提交
  7. 08 3月, 2016 2 次提交
  8. 26 2月, 2016 1 次提交
    • B
      PCI: Disable IO/MEM decoding for devices with non-compliant BARs · b84106b4
      Bjorn Helgaas 提交于
      The PCI config header (first 64 bytes of each device's config space) is
      defined by the PCI spec so generic software can identify the device and
      manage its usage of I/O, memory, and IRQ resources.
      
      Some non-spec-compliant devices put registers other than BARs where the
      BARs should be.  When the PCI core sizes these "BARs", the reads and writes
      it does may have unwanted side effects, and the "BAR" may appear to
      describe non-sensical address space.
      
      Add a flag bit to mark non-compliant devices so we don't touch their BARs.
      Turn off IO/MEM decoding to prevent the devices from consuming address
      space, since we can't read the BARs to find out what that address space
      would be.
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Tested-by: NAndi Kleen <ak@linux.intel.com>
      CC: stable@vger.kernel.org
      b84106b4
  9. 19 2月, 2016 1 次提交
  10. 18 2月, 2016 1 次提交
  11. 17 2月, 2016 1 次提交
  12. 06 2月, 2016 1 次提交
    • B
      PCI: Move pci_set_flags() from asm-generic/pci-bridge.h to linux/pci.h · 5bbe029f
      Bjorn Helgaas 提交于
      The PCI flag management constants and functions were previously declared in
      include/asm-generic/pci-bridge.h.  But they are not specific to bridges,
      and arches did not include pci-bridge.h consistently.
      
      Move the following interfaces and related constants to include/linux/pci.h
      and remove pci-bridge.h:
      
        pci_set_flags()
        pci_add_flags()
        pci_clear_flags()
        pci_has_flag()
      
      This fixes these warnings when building for some arches:
      
        drivers/pci/host/pcie-designware.c:562:20: error: 'PCI_PROBE_ONLY' undeclared (first use in this function)
        drivers/pci/host/pcie-designware.c:562:7: error: implicit declaration of function 'pci_has_flag' [-Werror=implicit-function-declaration]
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      5bbe029f
  13. 21 12月, 2015 1 次提交
  14. 26 11月, 2015 1 次提交
  15. 25 11月, 2015 1 次提交
    • G
      PCI/MSI: Initialize MSI capability for all architectures · e80e7edc
      Guilherme G. Piccoli 提交于
      1851617c ("PCI/MSI: Disable MSI at enumeration even if kernel doesn't
      support MSI") moved dev->msi_cap and dev->msix_cap initialization from the
      pci_init_capabilities() path (used on all architectures) to the
      pci_setup_device() path (not used on Open Firmware architectures).
      
      This broke MSI or MSI-X on Open Firmware machines.  4d9aac39
      ("powerpc/PCI: Disable MSI/MSI-X interrupts at PCI probe time in OF case")
      fixed it for PowerPC but not for SPARC.
      
      Set up MSI and MSI-X (initialize msi_cap and msix_cap and disable MSI and
      MSI-X) in pci_init_capabilities() so all architectures do it the same way.
      
      This reverts 4d9aac39 since this patch fixes the problem generically
      for both PowerPC and SPARC.
      
      [bhelgaas: changelog, make pci_msi_setup_pci_dev() static]
      Fixes: 1851617c ("PCI/MSI: Disable MSI at enumeration even if kernel doesn't support MSI")
      Signed-off-by: NGuilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      e80e7edc
  16. 23 10月, 2015 1 次提交
    • H
      PCI: Turn off Request Attributes to avoid Chelsio T5 Completion erratum · c56d4450
      Hariprasad Shenai 提交于
      The Chelsio T5 has a PCIe compliance erratum that causes Malformed TLP or
      Unexpected Completion errors in some systems, which may cause device access
      timeouts.
      
      Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same values
      for the Attribute as were supplied in the header of the corresponding
      Request, except as explicitly allowed when IDO is used."
      
      Instead of copying the Attributes from the Request to the Completion, the
      T5 always generates Completions with zero Attributes.  The receiver of a
      Completion whose Attributes don't match the Request may accept it (which
      itself seems non-compliant based on sec 2.3.2), or it may handle it as a
      Malformed TLP or an Unexpected Completion, which will probably lead to a
      device access timeout.
      
      Work around this by disabling "Relaxed Ordering" and "No Snoop" in the Root
      Port so it always generate Requests with zero Attributes.
      
      This does affect all other devices which are downstream of that Root Port,
      but these are performance optimizations that should not make a functional
      difference.
      
      Note that Configuration Space accesses are never supposed to have TLP
      Attributes, so we're safe waiting till after any Configuration Space
      accesses to do the Root Port "fixup".
      
      Based on original work by Casey Leedom <leedom@chelsio.com>
      
      [bhelgaas: changelog, comments, rename to pci_find_pcie_root_port(), rework
      to use pci_upstream_bridge() and check for Root Port device type, edit
      diagnostics to clarify intent and devices affected]
      Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      c56d4450
  17. 07 10月, 2015 1 次提交
    • P
      PCI: Add builtin_pci_driver() to avoid registration boilerplate · b4eb6cdb
      Paul Gortmaker 提交于
      In f309d444 ("platform_device: better support builtin boilerplate
      avoidance"), we introduced the builtin_driver() macro.
      
      Here we use that support and extend it to PCI driver registration, so where
      a driver is clearly non-modular and builtin-only, we can register it in a
      similar fashion.  Existing code that is clearly non-modular can be updated
      with the simple mapping of
      
        module_pci_driver(...)  ---> builtin_pci_driver(...)
      
      We've essentially cloned the former to make the latter, and taken out the
      remove/module_exit parts since those never get used in a non-modular build
      of the code.
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      b4eb6cdb
  18. 09 9月, 2015 1 次提交
  19. 26 8月, 2015 1 次提交
    • G
      PCI: Make pci_msi_setup_pci_dev() non-static for use by arch code · 22b6839b
      Guilherme G. Piccoli 提交于
      Commit 1851617c ("PCI/MSI: Disable MSI at enumeration even if kernel
      doesn't support MSI") changed the location of the code that initialises
      dev->msi_cap/msix_cap and then disables MSI/MSI-X interrupts at PCI
      probe time in devices that have this flag set. It moved the code from
      pci_msi_init_pci_dev() to a new function named pci_msi_setup_pci_dev(),
      called by pci_setup_device().
      
      The pseries PCI probing code does not call pci_setup_device(), so since
      the aforementioned commit the function pci_msi_setup_pci_dev() is not
      called and MSI/MSI-X interrupts are left enabled. Additionally because
      dev->msi_cap/msix_cap are not initialised no driver can ever enable
      MSI/MSI-X.
      
      To fix this, the pseries PCI probe should manually call
      pci_msi_setup_pci_dev(), so this patch makes it non-static.
      
      Fixes: 1851617c ("PCI/MSI: Disable MSI at enumeration even if kernel doesn't support MSI")
      [mpe: Update change log to mention dev->msi_cap/msix_cap]
      Signed-off-by: NGuilherme G. Piccoli <gpiccoli@linux.vnet.ibm.com>
      Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
      22b6839b
  20. 25 8月, 2015 1 次提交
    • L
      PCI: Add pci_ioremap_wc_bar() · c43996f4
      Luis R. Rodriguez 提交于
      This lets drivers take advantage of PAT when available. It
      should help with the transition of converting video drivers over
      to ioremap_wc() to help with the goal of eventually using
      _PAGE_CACHE_UC over _PAGE_CACHE_UC_MINUS on x86 on
      ioremap_nocache(), see:
      
        de33c442 ("x86 PAT: fix performance drop for glx, use UC minus for ioremap(), ioremap_nocache() and pci_mmap_page_range()")
      Signed-off-by: NLuis R. Rodriguez <mcgrof@suse.com>
      Signed-off-by: NBorislav Petkov <bp@suse.de>
      Acked-by: NArnd Bergmann <arnd@arndb.de>
      Cc: <syrjala@sci.fi>
      Cc: Andrew Morton <akpm@linux-foundation.org>
      Cc: Andy Lutomirski <luto@amacapital.net>
      Cc: Antonino Daplas <adaplas@gmail.com>
      Cc: Bjorn Helgaas <bhelgaas@google.com>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Dave Airlie <airlied@redhat.com>
      Cc: Davidlohr Bueso <dbueso@suse.de>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Cc: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
      Cc: Juergen Gross <jgross@suse.com>
      Cc: Linus Torvalds <torvalds@linux-foundation.org>
      Cc: Mel Gorman <mgorman@suse.de>
      Cc: Peter Zijlstra <peterz@infradead.org>
      Cc: Suresh Siddha <sbsiddha@gmail.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
      Cc: Toshi Kani <toshi.kani@hp.com>
      Cc: Ville Syrjälä <syrjala@sci.fi>
      Cc: Vlastimil Babka <vbabka@suse.cz>
      Cc: airlied@linux.ie
      Cc: benh@kernel.crashing.org
      Cc: dan.j.williams@intel.com
      Cc: konrad.wilk@oracle.com
      Cc: linux-fbdev@vger.kernel.org
      Cc: linux-pci@vger.kernel.org
      Cc: mst@redhat.com
      Cc: vinod.koul@intel.com
      Cc: xen-devel@lists.xensource.com
      Link: http://lkml.kernel.org/r/1440443613-13696-2-git-send-email-mcgrof@do-not-panic.comSigned-off-by: NIngo Molnar <mingo@kernel.org>
      c43996f4
  21. 24 8月, 2015 1 次提交
    • K
      PCI: Set MPS to match upstream bridge · 27d868b5
      Keith Busch 提交于
      Firmware typically configures the PCIe fabric with a consistent Max Payload
      Size setting based on the devices present at boot.  A hot-added device
      typically has the power-on default MPS setting (128 bytes), which may not
      match the fabric.
      
      The previous Linux default, in the absence of any "pci=pcie_bus_*" options,
      was PCIE_BUS_TUNE_OFF, in which we never touch MPS, even for hot-added
      devices.
      
      Add a new default setting, PCIE_BUS_DEFAULT, in which we make sure every
      device's MPS setting matches the upstream bridge.  This makes it more
      likely that a hot-added device will work in a system with optimized MPS
      configuration.
      
      Note that if we hot-add a device that only supports 128-byte MPS, it still
      likely won't work because we don't reconfigure the rest of the fabric.
      Booting with "pci=pcie_bus_peer2peer" is a workaround for this because it
      sets MPS to 128 for everything.
      
      [bhelgaas: changelog, new default, rework for pci_configure_device() path]
      Tested-by: NKeith Busch <keith.busch@intel.com>
      Tested-by: NJordan Hargrave <jharg93@gmail.com>
      Signed-off-by: NKeith Busch <keith.busch@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NYinghai Lu <yinghai@kernel.org>
      27d868b5
  22. 21 8月, 2015 1 次提交
  23. 14 8月, 2015 6 次提交
  24. 31 7月, 2015 4 次提交
  25. 30 7月, 2015 1 次提交
  26. 23 7月, 2015 1 次提交
  27. 22 7月, 2015 1 次提交
    • M
      PCI: Add dev_flags bit to access VPD through function 0 · 932c435c
      Mark Rustad 提交于
      Add a dev_flags bit, PCI_DEV_FLAGS_VPD_REF_F0, to access VPD through
      function 0 to provide VPD access on other functions.  This is for hardware
      devices that provide copies of the same VPD capability registers in
      multiple functions.  Because the kernel expects that each function has its
      own registers, both the locking and the state tracking are affected by VPD
      accesses to different functions.
      
      On such devices for example, if a VPD write is performed on function 0,
      *any* later attempt to read VPD from any other function of that device will
      hang.  This has to do with how the kernel tracks the expected value of the
      F bit per function.
      
      Concurrent accesses to different functions of the same device can not only
      hang but also corrupt both read and write VPD data.
      
      When hangs occur, typically the error message:
      
        vpd r/w failed.  This is likely a firmware bug on this device.
      
      will be seen.
      
      Never set this bit on function 0 or there will be an infinite recursion.
      Signed-off-by: NMark Rustad <mark.d.rustad@intel.com>
      Signed-off-by: NBjorn Helgaas <bhelgaas@google.com>
      Acked-by: NAlexander Duyck <alexander.h.duyck@redhat.com>
      CC: stable@vger.kernel.org
      932c435c
  28. 13 6月, 2015 1 次提交