1. 24 1月, 2015 2 次提交
  2. 22 1月, 2015 1 次提交
  3. 20 1月, 2015 2 次提交
  4. 19 1月, 2015 1 次提交
  5. 18 1月, 2015 2 次提交
    • T
      ARM: mvebu: completely disable hardware I/O coherency · 8f1e8ee2
      Thomas Petazzoni 提交于
      The current hardware I/O coherency is known to cause problems with DMA
      coherent buffers, as it still requires explicit I/O synchronization
      barriers, which is not compatible with the semantics expected by the
      Linux DMA coherent buffers API.
      
      So, in order to have enough time to validate a new solution based on
      automatic I/O synchronization barriers, this commit disables hardware
      I/O coherency entirely. Future patches will re-enable it.
      Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Cc: <stable@vger.kernel.org> # v3.8+
      Signed-off-by: NAndrew Lunn <andrew@lunn.ch>
      8f1e8ee2
    • M
      ARM: OMAP: Work around hardcoded interrupts · 0fb22a8f
      Marc Zyngier 提交于
      Commit 9a1091ef ("irqchip: gic: Support hierarchy irq domain")
      changed the GIC driver to use a non-legacy IRQ domain on DT
      platforms. This patch assumes that DT-driven systems are getting
      all of their interrupts from device tree.
      
      Turns out that OMAP has quite a few hidden gems, and still uses
      hardcoded interrupts despite having fairly complete DTs.
      
      This patch attempts to work around these by offering a translation
      method that can be called directly from the hwmod code, if present.
      The same hack is sprinkled over PRCM and TWL.
      
      It isn't pretty, but it seems to do the job without having to add
      more hacks to the interrupt controller code.
      
      Tested on OMAP4 (Panda-ES) and OMAP5 (UEVM5432).
      Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
      Acked-by: NNishanth Menon <nm@ti.com>
      [tony@atomide.com: updated to fix make randconfig issue]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      0fb22a8f
  6. 17 1月, 2015 14 次提交
  7. 16 1月, 2015 1 次提交
  8. 12 1月, 2015 14 次提交
  9. 11 1月, 2015 3 次提交