Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
1 年多 前同步成功

通知 160
Star 36
Fork 7
cloud-kernel
cloud-kernel
切换分支/标签
  1. 07 3月, 2015 1 次提交
  3. 20 2月, 2015 1 次提交
  5. 18 2月, 2015 4 次提交
  7. 17 2月, 2015 1 次提交
  9. 14 2月, 2015 5 次提交
    • G
      rtc: armada38x: add the device tree binding documentation · bb624047
      由 Gregory CLEMENT 提交于 
      The Marvell Armada 38x SoCs contains an RTC which differs from the RTC
used in the other mvebu SoCs until now.  This forth version of the patch
set adds support for this new IP and enable it in the Device Tree of the
Armada 38x SoC.

This patch (of 5):

The Armada 38x SoCs come with a new RTC which differs from the one used in
the other mvebu SoCs until now.  This patch describes the binding of this
RTC.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Cc: Arnaud Ebalard <arno@natisbad.org>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Boris BREZILLON <boris.brezillon@free-electrons.com>
Cc: Lior Amsalem <alior@marvell.com>
Cc: Tawfik Bayouk <tawfik@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      bb624047
    • A
      rtc: add support for Abracon AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC chip · 0b2f6228
      由 Arnaud Ebalard 提交于 
      This patch adds support for Abracon AB-RTCMC-32.768kHz-B5ZE-S3
RTC/Calendar module w/ I2C interface.

This support includes RTC time reading and setting, Alarm (1 minute
accuracy) reading and setting, and battery low detection.  The device also
supports frequency adjustment and two timers but those features are
currently not implemented in this driver.  Due to alarm accuracy
limitation (and current lack of timer support in the driver), UIE mode is
not supported.
Signed-off-by: NArnaud Ebalard <arno@natisbad.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Peter Huewe <peter.huewe@infineon.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Landley <rob@landley.net>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      0b2f6228
    • A
      of: add vendor prefix for Abracon Corporation · 446810f2
      由 Arnaud Ebalard 提交于 
      This series adds support for Abracon AB-RTCMC-32.768kHz-B5ZE-S3 I2C RTC
chip. Unlike many RTC chips, it includes an internal oscillator which
spares room on the PCB. It also has some interesting features, like
battery low detection (which the driver in this series supports). The
only small "limitation" (mainly due to what RTC subsystem expects from
RTC chips) is the fact that its alarm is accurate to the second. This
series provides a solution (described below) for that limitation using
another mechanism of the chip.

I decided to split support between three different patches for
this v0:

- Patch 1/3: it simply references Abracon Corporation in vendor-prefixes
  documentation file. As Abracon has no NASDAQ ticker symbol; I have
  decided to use "abcn" (I initially started my work w/ "ab" but later
  changed for "abcn" which looked more meaningful)
- Patch 2/3: it adds initial support for the chip and provides the
  ability to read/write time and also read/write alarm. As the alarm
  the chip provides is accurate to the minute, the support provided
  by this patch also has this limitation (e.g. UIE mode is not
  supported).
- Patch 3/3: the chip supports a watchdog timer which can be used to
  extend the alarm mechanism in patch 2/3 in order to provide support
  for alarms under one minute (e.g. support UIE mode). In practice,
  the logic I implemented is to use the watchdog timer for alarms which
  are at most 4 minutes in the future and use the common alarm mechanism
  for alarms which are set to larger values. With that additional patch
  the device fully passes the rtctest.c program.

I decided to split the driver between two patches (2 and 3 of 3) in
order to ease review: patch 2 should be pretty straightforward to read
for someone familiar w/ RTC subsystem. Patch 3 only extends what is in
patch 2 regarding alarms.

This patch (of 3):

Documentation/devicetree/bindings/vendor-prefixes.txt: add vendor prefix
for Abracon Corporation
Signed-off-by: NArnaud Ebalard <arno@natisbad.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Peter Huewe <peter.huewe@infineon.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Landley <rob@landley.net>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Kumar Gala <galak@codeaurora.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      446810f2
    • A
      rtc: rtc-isl12057: add isil,irq2-can-wakeup-machine property for in-tree users · 298ff012
      由 Arnaud Ebalard 提交于 
      Current in-tree users of ISL12057 RTC chip (NETGEAR ReadyNAS 102, 104 and
2120) do not have the IRQ#2 pin of the chip (associated w/ the Alarm1
mechanism) connected to their SoC, but to a PMIC (TPS65251 FWIW).  This
specific hardware configuration allows the NAS to wake up when the alarms
rings.

Recently introduced alarm support for ISL12057 relies on the provision of
an "interrupts" property in system .dts file, which previous three users
will never get.  For that reason, alarm support on those devices is not
function.  To support this use case, this patch adds a new DT property for
ISL12057 (isil,irq2-can-wakeup-machine) to indicate that the chip is
capable of waking up the device using its IRQ#2 pin (even though it does
not have its IRQ#2 pin connected directly to the SoC).

This specific configuration was tested on a ReadyNAS 102 by setting an
alarm, powering off the device and see it reboot as expected when the
alarm rang w/:

  # echo `date '+%s' -d '+ 1 minutes'` > /sys/class/rtc/rtc0/wakealarm
  # shutdown -h now

As a side note, the ISL12057 remains in the list of trivial devices,
because the property is not per se required by the device to work but can
help handle system w/ specific requirements.  In exchange, the new feature
is described in details in a specific documentation file.
Signed-off-by: NArnaud Ebalard <arno@natisbad.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Peter Huewe <peter.huewe@infineon.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Darshana Padmadas <darshanapadmadas@gmail.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Landley <rob@landley.net>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Guenter Roeck <linux@roeck-us.net>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Uwe Kleine-König <uwe@kleine-koenig.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      298ff012
    • J
      drivers/rtc/rtc-pcf2123.c: add support for devicetree · 3fc70077
      由 Joshua Clayton 提交于 
      Add compatible string "nxp,rtc-pcf2123"
Document the binding
Signed-off-by: NJoshua Clayton <stillcompiling@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Grant Likely <grant.likely@linaro.org>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      3fc70077
  11. 11 2月, 2015 1 次提交
  13. 08 2月, 2015 1 次提交
  15. 07 2月, 2015 2 次提交
  17. 06 2月, 2015 3 次提交
  19. 05 2月, 2015 9 次提交
  21. 04 2月, 2015 7 次提交
    • T
      Doc/DT: Add DT binding doc for DRA7xx DSS · 6761a8f6
      由 Tomi Valkeinen 提交于 
      Add device tree binding documentation for DRA7xx display subsystem.
Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
Cc: devicetree@vger.kernel.org
      6761a8f6
    • M
      mmc: pwrseq: add driver for emmc hardware reset · 726b6324
      由 Marek Szyprowski 提交于 
      This patch provides a simple mmc-pwrseq-emmc driver, which controls
single gpio line. It perform standard eMMC hw reset procedure, as
descibed by Jedec 4.4 specification. This procedure is performed just
after MMC core enabled power to the given mmc host (to fix possible
issues if bootloader has left eMMC card in initialized or unknown
state), and before performing complete system reboot (also in case of
emergency reboot call). The latter is needed on boards, which doesn't
have hardware reset logic connected to emmc card and (limited or broken)
ROM bootloaders are unable to read second stage from the emmc card if
the card is left in unknown or already initialized state.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
      726b6324
    • P
      Documentation: DT: document compatible string existence requirement · 10638a4e
      由 Paul Walmsley 提交于 
      DT maintainers require all compatible strings used in chip or board
DTS file to be previously documented somewhere in
Documentation/devicetree/bindings, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

Document this requirement in the DT patch submission requirements
text file.

This second version updates the documentation to align with
Rob's comments here:

http://marc.info/?l=devicetree&m=142255654213019&w=2Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NRob Herring <robh@kernel.org>
      10638a4e
    • P
      Documentation: DT bindings: add nvidia, tegra132-denver compatible string · f634da37
      由 Paul Walmsley 提交于 
      Add a compatible string for the NVIDIA Denver CPU to the ARM CPU DT
binding documentation file.  The primary objective here is to keep
checkpatch.pl from warning when the compatible string is used in an
SoC DT file, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

This second version changes the string from "nvidia,denver" to
"nvidia,tegra132-denver" to more precisely describe the revision of
the Denver CPU complex that is present in the Tegra132 SoC.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Rohit Vaswani <rvaswani@codeaurora.org>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Marc Carino <marc.ceeeee@gmail.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NRob Herring <robh@kernel.org>
      f634da37
    • P
      Documentation: DT bindings: add more Tegra chip compatible strings · 193c9d23
      由 Paul Walmsley 提交于 
      Align compatible strings for several IP blocks present on Tegra chips
with the latest doctrine from the DT maintainers:

http://marc.info/?l=devicetree&m=142255654213019&w=2

The primary objective here is to avoid checkpatch warnings, per:

http://marc.info/?l=linux-tegra&m=142201349727836&w=2

DT binding text files have been updated for the following IP blocks:

- PCIe
- SOR
- SoC timers
- AHB "gizmo"
- APB_MISC
- pinmux control
- UART
- PWM
- I2C
- SPI
- RTC
- PMC
- eFuse
- AHCI
- HDA
- XUSB_PADCTRL
- SDHCI
- SOC_THERM
- AHUB
- I2S
- EHCI
- USB PHY

N.B. The nvidia,tegra20-timer compatible string is removed from the
nvidia,tegra30-timer.txt documentation file because it's already
mentioned in the nvidia,tegra20-timer.txt documentation file.

This second version takes into account the following requests from
Rob Herring <robherring2@gmail.com>:

- Per-IP block patches have been combined into a single patch

- Explicit documentation about which compatible strings are actually
  matched by the driver has been removed.  In its place is implicit
  documentation that loosely follows Rob's prescribed format:

  "Must contain '"nvidia,<chip>-pcie", "nvidia,tegra20-pcie"' where
   <chip> is tegra30, tegra132, ..." [...]  "You should attempt to
   document known values of <chip> if you use it"
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Dylan Reid <dgreid@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Jingchang Lu <jingchang.lu@freescale.com>
Cc: John Crispin <blogic@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Peter Hurley <peter@hurleysoftware.com>
Cc: Sean Paul <seanpaul@chromium.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Takashi Iwai <tiwai@suse.de>
Cc: Tejun Heo <tj@kernel.org>
Cc: "Terje Bergström" <tbergstrom@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Cc: Wolfram Sang <wsa@the-dreams.de>
Cc: Zhang Rui <rui.zhang@intel.com>
Cc: dri-devel@lists.freedesktop.org
Cc: linux-i2c@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: linux-pm@vger.kernel.org
Cc: linux-pwm@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Acked-by: NEduardo Valentin <edubezval@gmail.com>
Signed-off-by: NRob Herring <robh@kernel.org>
      193c9d23
    • S
      net/fsl_pq_mdio: Document supported compatibles · 132d7bca
      由 Shruti Kanetkar 提交于 
      The device tree binding(s) document has fallen out of sync with the
driver code. Update the list of supported devices to reflect current
driver capabilities

Change-Id: I440d8de2ee2d9c3b7b23e69b3da851cab18a4c9a
Signed-off-by: NShruti Kanetkar <Kanetkar.Shruti@gmail.com>
Signed-off-by: NEmil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      132d7bca
    • V
      Input: ti_am335x_tsc - read charge delay from DT · bf223612
      由 Vignesh R 提交于 
      This patch reads charge delay from tsc DT node and writes to
REG_CHARGEDELAY register. If the charge delay is not specified in DT then
default value of 0x400(CHARGEDLY_OPENDLY) is used.
Signed-off-by: NVignesh R <vigneshr@ti.com>
Signed-off-by: NDmitry Torokhov <dmitry.torokhov@gmail.com>
      bf223612
  23. 03 2月, 2015 3 次提交
  25. 02 2月, 2015 2 次提交