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  1. 16 10月, 2013 3 次提交
  3. 30 8月, 2013 1 次提交
  5. 21 8月, 2013 1 次提交
  7. 20 8月, 2013 1 次提交
  9. 13 8月, 2013 1 次提交
  11. 07 8月, 2013 2 次提交
  13. 01 8月, 2013 1 次提交
    • S
      Documentation: Add memory mapped ARM architected timer binding · d53ef114
      由 Stephen Boyd 提交于 
      Add a binding for the arm architected timer hardware's memory
mapped interface. The mmio timer hardware is made up of one base
frame and a collection of up to 8 timer frames, where each of the
8 timer frames can have either one or two views. A frame
typically maps to a privilege level (user/kernel, hypervisor,
secure). The first view has full access to the registers within a
frame, while the second view can be restricted to particular
registers within a frame. Each frame must support a physical
timer. It's optional for a frame to support a virtual timer.

Cc: devicetree-discuss@lists.ozlabs.org
Cc: Marc Zyngier <Marc.Zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Herring <robherring2@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
Acked-by: NMark Rutland <mark.rutland@arm.com>
      d53ef114
  15. 25 7月, 2013 2 次提交
  17. 03 7月, 2013 1 次提交
    • S
      clocksource: arm_global_timer: Add ARM global timer support · c1b40e44
      由 Stuart Menefy 提交于 
      This is a simple driver for the global timer module found in the Cortex
A9-MP cores from revision r1p0 onwards. This should be able to perform
the functions of the system timer and the local timer in an SMP system.

The global timer has the following features:
    The global timer is a 64-bit incrementing counter with an
auto-incrementing feature. It continues incrementing after sending
interrupts. The global timer is memory mapped in the private memory
region.
    The global timer is accessible to all Cortex-A9 processors in the
cluster. Each Cortex-A9 processor has a private 64-bit comparator that
is used to assert a private interrupt when the global timer has reached
the comparator value. All the Cortex-A9 processors in a design use the
banked ID, ID27, for this interrupt. ID27 is sent to the Interrupt
Controller as a Private Peripheral Interrupt. The global timer is
clocked by PERIPHCLK.
Signed-off-by: NStuart Menefy <stuart.menefy@st.com>
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@st.com>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Rob Herring <robherring2@gmail.com>
CC: Linus Walleij <linus.walleij@linaro.org>
CC: Will Deacon <will.deacon@arm.com>
CC: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: NDaniel Lezcano <daniel.lezcano@linaro.org>
      c1b40e44
  19. 22 6月, 2013 1 次提交
  21. 19 6月, 2013 1 次提交
  23. 18 6月, 2013 1 次提交
  25. 17 6月, 2013 2 次提交
    • L
      ARM: u300: add syscon node · cf0ce095
      由 Linus Walleij 提交于 
      This adds a device tree node for the U300 system controller
and remaps this dynamically instead of using hard-coded
virtual addresses. The board power set-up code is altered
to fetch a reference to the syscon using ampersand <&syscon>
notation. This way of passing a pointer to the syscon will
also be used by the clocks.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      cf0ce095
    • L
      ARM: u300: set up board power from device tree · 4d3ab5ec
      由 Linus Walleij 提交于 
      This adds support for setting up the board power from the
device tree on the U300. We use a board-specific node in the
device tree for the S365 board and bind a regulator for the
board power to this node.

Cc: Mark Brown <broonie@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
      4d3ab5ec
  27. 31 5月, 2013 1 次提交
  29. 30 5月, 2013 2 次提交
    • N
      ARM: vexpress: introduce DCSCB support · 1e904e1b
      由 Nicolas Pitre 提交于 
      This adds basic CPU and cluster reset controls on RTSM for the
A15x4-A7x4 model configuration using the Dual Cluster System
Configuration Block (DCSCB).

The cache coherency interconnect (CCI) is not handled yet.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: NPawel Moll <pawel.moll@arm.com>
      1e904e1b
    • L
      drivers: bus: add ARM CCI support · ed69bdd8
      由 Lorenzo Pieralisi 提交于 
      On ARM multi-cluster systems coherency between cores running on
different clusters is managed by the cache-coherent interconnect (CCI).
It allows broadcasting of TLB invalidates and memory barriers and it
guarantees cache coherency at system level through snooping of slave
interfaces connected to it.

This patch enables the basic infrastructure required in Linux to handle and
programme the CCI component.

Non-local variables used by the CCI management functions called by power
down function calls after disabling the cache must be flushed out to main
memory in advance, otherwise incoherency of those values may occur if they
are sitting in the cache of some other CPU when power down functions
execute. Driver code ensures that relevant data structures are flushed
from inner and outer caches after the driver probe is completed.

CCI slave port resources are linked to set of CPUs through bus masters
phandle properties that link the interface resources to masters node in
the device tree.

Documentation describing the CCI DT bindings is provided with the patch.
Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NNicolas Pitre <nicolas.pitre@linaro.org>
      ed69bdd8
  31. 28 5月, 2013 1 次提交
  33. 16 5月, 2013 1 次提交
  35. 13 5月, 2013 1 次提交
  37. 15 4月, 2013 1 次提交
    • D
      ARM: socfpga: Add clock entries into device tree · 042000b0
      由 Dinh Nguyen 提交于 
      Adds the main PLL clock groups for SOCFPGA into device tree file
so that the clock framework to query the clock and clock rates
appropriately.

$cat /sys/kernel/debug/clk/clk_summary
   clock                        enable_cnt  prepare_cnt  rate
---------------------------------------------------------------------
 osc1                           2           2            25000000
    sdram_pll                   0           0            400000000
       s2f_usr2_clk             0           0            66666666
       ddr_dq_clk               0           0            200000000
       ddr_2x_dqs_clk           0           0            400000000
       ddr_dqs_clk              0           0            200000000
    periph_pll                  2           2            500000000
       s2f_usr1_clk             0           0            50000000
       per_base_clk             4           4            100000000
       per_nand_mmc_clk         0           0            25000000
       per_qsi_clk              0           0            250000000
       emac1_clk                1           1            125000000
       emac0_clk                0           0            125000000
    main_pll                    1           1            1600000000
       cfg_s2f_usr0_clk         0           0            100000000
       main_nand_sdmmc_clk      0           0            100000000
       main_qspi_clk            0           0            400000000
       dbg_base_clk             0           0            400000000
       mainclk                  0           0            400000000
       mpuclk                   1           1            800000000
          smp_twd               1           1            200000000
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      042000b0
  39. 09 4月, 2013 4 次提交
  41. 04 4月, 2013 2 次提交
  43. 03 4月, 2013 4 次提交
  45. 29 3月, 2013 2 次提交
  47. 26 3月, 2013 1 次提交
  49. 23 3月, 2013 1 次提交
    • S
      ARM: msm: Rework timer binding to be more general · eebdb0c1
      由 Stephen Boyd 提交于 
      The msm timer binding I wrote is bad. First off, the clock
frequency in the binding for the dgt is wrong. Software divides
down the input rate by 4 to achieve the rate listed in the
binding. We also treat each individual timer as a separate
hardware component, when in reality there is one timer block
(that may be duplicated per cpu) with multiple timers within it.
Depending on the version of the hardware there can be one or two
general purpose timers, status and divider control registers, and
an entirely different register layout.

In the next patch we'll need to know about the different register
layouts so that we can properly check the status register after
clearing the count. The current binding makes this complicated
because the general purpose timer's reg property doesn't indicate
where that status register is, and in fact it is beyond the size
of the reg property.

Clean all this up by just having one node for the timer hardware,
and describe all the interrupts and clock frequencies supported
while having one reg property that covers the entire timer
register region. We'll use the compatible field in the future to
determine different register layouts and if we should read the
status registers, etc.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
      eebdb0c1
  51. 18 3月, 2013 1 次提交