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  1. 12 10月, 2017 1 次提交
  3. 30 8月, 2017 1 次提交
  5. 19 8月, 2017 1 次提交
  7. 16 8月, 2017 4 次提交
  9. 14 8月, 2017 9 次提交
  11. 12 8月, 2017 1 次提交
  13. 03 8月, 2017 1 次提交
    • M
      arm64: defconfig: enable fine-grained task level IRQ time accounting · a168f2a8
      由 Marcin Wojtas 提交于 
      Tests showed, that under certain conditions, the summary number of jiffies
spent on softirq/idle, which are counted by system statistics can be even
below 10% of expected value, resulting in false load presentation.

The issue was observed on the quad-core Marvell Armada 8k SoC, whose two
10G ports were bound into L2 bridge. Load was controlled by bidirectional
UDP traffic, produced by a packet generator. Under such condition,
the dominant load is softirq. With 100% single CPU occupation or without
any activity (all CPUs 100% idle), total number of jiffies is 10000 (2500
per each core) in 10s interval. Also with other kind of load this was
true.

However below a saturation threshold it was observed, that with CPU which
was occupied almost by softirqs only, the statistic were awkward. See
the mpstat output:

CPU %usr %nice %sys %iowait %irq %soft %steal %guest %gnice %idle
all 0.00  0.00 0.13    0.00 0.00  0.55   0.00   0.00   0.00 99.32
  0 0.00  0.00 0.00    0.00 0.00 23.08   0.00   0.00   0.00 76.92
  1 0.00  0.00 0.40    0.00 0.00  0.00   0.00   0.00   0.00 99.60
  2 0.00  0.00 0.00    0.00 0.00  0.00   0.00   0.00   0.00 100.00
  3 0.00  0.00 0.00    0.00 0.00  0.00   0.00   0.00   0.00 100.00

Above would mean basically no total load, debug CPU0 occupied in 25%.
Raw statistics, printed every 10s from /proc/stat unveiled a root
cause - summary idle/softirq jiffies on loaded CPU were below 200,
i.e. over 90% samples lost. All problems were gone after enabling
fine granulity IRQ time accounting.

This patch fixes possible wrong statistics processing by enabling
CONFIG_IRQ_TIME_ACCOUNTING for arm64 platfroms, which is by
default done on other architectures, e.g. x86 and arm. Tests
showed no noticeable performance penalty, nor stability impact.
Signed-off-by: NMarcin Wojtas <mw@semihalf.com>
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
      a168f2a8
  15. 28 7月, 2017 1 次提交
  17. 27 7月, 2017 1 次提交
  19. 18 7月, 2017 1 次提交
  21. 02 7月, 2017 1 次提交
  23. 26 6月, 2017 1 次提交
  25. 23 6月, 2017 8 次提交
  27. 15 6月, 2017 2 次提交
  29. 12 6月, 2017 1 次提交
  31. 09 6月, 2017 1 次提交
  33. 02 6月, 2017 2 次提交
  35. 26 5月, 2017 1 次提交
    • H
      arm64: defconfig: enable some core options for 64bit Rockchip socs · 5711ea1b
      由 Heiko Stuebner 提交于 
      Enable some very core config options used on 64bit Rockchip socs.

As built-in driver enable the Rockchip spi driver as well as the
cros-ec-spi and cros-ec keyboard driver, as this may be helpful
in case an initrd does not work as expected and drops the user
into a shell. Another built-in is the fan53555 regulator driver,
as it and its register-compatible cousins Silergy syr827 and syr828
are often used on Rockchip socs as cpu-supply next to regular pmic.

The rest can be enabled as modules and contains the pcie host
controller and its phy, the sucessive approximation adc (saradc)
that gets often used for additional buttons on Rockchip boards
as well as the adc-keys Keyboard driver for these keys.

The cros-ec-pwm also can be a module, as it is normally only used to
drive display backlights as well as the Rockchip thermal controller
that allows to read the cpu and gpu temperatures and affect frequency
scaling if necessary.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>
      5711ea1b
  37. 19 5月, 2017 2 次提交