Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device
tree
Signed-off-by: NJon Mason <jon.mason@broadcom.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: NDuc Dang <dhdang@apm.com>
Acked-by: NCarlo Caione <carlo@endlessm.com>
Acked-by: NMichal Simek <michal.simek@xilinx.com>
Acked-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMasahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add device tree entry for PWM support for Broadcom Northstar 2 SoC.
Signed-off-by: NYendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add integrated MDIO multiplexer driver node which contains
two mux PCIe bus and one ethernet bus along with phys
lying on these bus.
Signed-off-by: NPramod Kumar <pramod.kumar@broadcom.com>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>

Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU.
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add all of the UARTs present on NS2 and enable them in the SVK device
tree file.  Also, do some magic to make sure that uart3 is discovered as
ttyS0 (as that is the console UART).
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

This enables the GPIO support for Broadcom NS2 SoC
Signed-off-by: NYendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

This enables the pinctrl support for Broadcom NS2 SoC
Signed-off-by: NYendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: NRay Jui <ray.jui@broadcom.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We have one dual-port SATA3 AHCI controller present in
NS2 SoC.

This patch enables SATA3 AHCI controller and SATA3 PHY
for NS2 SoC in NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Declare PSCI-1.0 node and enable CPU_ON method via PSCI.  Spin-table
memreserve has been removed as well as syscon based reset, as PSCI-1.0
expects reset implementation in firmware.
Signed-off-by: NLuke Starrett <luke.starrett@broadcom.com>
Acked-by: NScott Branden <scott.branden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We have two ARM PL022 SPI instances in NS2 SoC. On NS2 SVK,
one of the ARM PL022 SPI host has Silabs si3226x slic connected
to chip-select #0 whereas second ARM PL022 SPI host has Atmel
AT25 EEPROM connected to chip-select #0.

This patch adds ARM PL022, Silabs si3226x, and Atmel AT25
DT nodes in NS2 DT and NS2 SVK DT respectively.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

For more readabilty and consistency with other Broadcom SoCs, we move
all NS2 clock DT nodes from main SoC DT file to a separate DT file.

We also update the license header in ns2.dtsi as-per new Broadcom
convention.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The KVM ARM64 requires GIC maintenance interrupt for VGIC emulation
so this patch adds the missing "interrupts" attribute to GIC node in
NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We have one ARM PL330 DMA instance with 8 channels in
NS2 SoC. Let's enable it for NS2 in NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NPramod KUMAR <pramodku@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

This patch enables PCIe0 and PCIe4 for NS2 by adding
appropriate DT nodes in NS2 DT.
Signed-off-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We have one ARM SP805 watchdog instance on NS2 for non-secure software
hence this patch adds appropriate watchdog DT node in NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NPramod KUMAR <pramodku@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We have four ARM SP804 dual-mode timer instances in NS2 SoC
hence this patch adds appropriate DT nodes for NS2.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NPramod KUMAR <pramodku@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The IPROC SDHCI driver works fine for SDIO 3.0 on NS2 so let's enable
it for NS2 SoC in NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add device tree entries for clock support for Broadcom Northstar 2 SoC
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The NAND controller on NS2 SoC is compatible with existing
BRCM IPROC NAND driver so let's enable it in NS2 DT and
NS2 SVK DT.

This patch also fixes use of node labels in ns2-svk.dts.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Reviewed-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

This patch adds iProc I2C DT nodes for NS2 and enable them for the NS2
SVK board
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

We have IPROC RNG200 hardware random number generation in
NS2 SoC, lets enable it for NS2 in NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NPramod KUMAR <pramodku@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The NS2 SoC has Cortex-A57 CPUs which support ARM PMUv3 so,
lets enable ARM PMUv3 in NS2 DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NVikram Prakash <vikramp@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

To reset NS2, we simply have to write '0' to BIT[1] at offset 0x90
of CRMU space.

The above can be easily achieved by writing 0xfffffffd at offset 0x90
using syscon-reboot driver. We don't need to have separate driver for
rebooting NS2.

This patch enables syscon-reboot driver for NS2 using DT.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

The SMMU-500 driver is already available in Linux kernel. Let's
enable it for NS2 in DT.

This patch keeps mmu-masters attribute empty so that driver patches
can later extend this attribute when adding device DT nodes.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Recent kernels requires cache hierrachy to be defined via DT hence
this patch updates NS2 DT accordingly.
Signed-off-by: NAnup Patel <anup.patel@broadcom.com>
Reviewed-by: NSandeep Tripathy <tripathy@broadcom.com>
Reviewed-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>

Add Broadcom NS2 device tree binding document. Also add initial device
tree dtsi for Broadcom North Star 2 (NS2) SoC and board support for NS2
SVK board
Signed-off-by: NJon Mason <jonmason@broadcom.com>
Signed-off-by: NRay Jui <rjui@broadcom.com>
Reviewed-by: NScott Branden <sbranden@broadcom.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>