First Ethernet device has a ".0" appended onto the device name. It
appears that we need this in order to obtain the correct clock.

Without this fix Ethernet does not function on Ux500 devices, which is a
regression.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved changelog]

AC97 controller clock is hardwired to pll_a_out0.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The USB clocks are just clock gates, so no need to set a specific clock.
In fact trying to set a specific clock is just a NOP if the requested
clockrate is the same as those of the parent (clk_m) or will trigger a
WARN_ON() if rates don't match up.

As we are not setting a specific rate, nor activating the clocks at
init, there is no point in keeping the the usb entries in the clock init
table.
Signed-off-by: NLucas Stach <dev@lynxeye.de>
Acked-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Tested-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The DMA controller in Lynxpoint is enumerated as a regular ACPI device now. To
work properly it is using the LPSS root clock as a functional clock. That's why
we have to register the clock device accordingly to the ACPI ID of the DMA
controller. The acpi_lpss.c module is responsible to do the job.

This patch also removes hardcoded name of the DMA device in clk-lpt.c and the
name of the root clock in acpi_lpss.c.
Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This is primarily useful when there's a driver that doesn't claim clocks
properly, but the bootloader leaves them on. It's not expected to be used
in normal cases, but for bringup and debug it's very useful to have the
option to not gate unclaimed clocks that are still on.
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up trivial merge issue]

commit 688f7d8c ("clk: exynos5250: Fix divider values for
sclk_mmc{0,1,2,3}") incorrectly sets the divider for sclk_mmc{0,1,2,3}
to fix the wrong clock value. Though this fixed issue with Arndale,
it created regressions for other boards like Snow.

On Exynos5250, sclk_mmc<n> is generated like below (as per the clock
names in drivers/clk/samsung/clk-exynos5250.c)

mout_group1_p ==> mout_mmc<n> ==>
		div_mmc<n> ==> div_mmc_pre<n> => sclk_mmc<n>

Earlier div_mmc<n> was set as the parent for sclk_mmc<n>, hence
div_mmc_pre<n> was not getting referred in kernel code and depending
on its value set during preboot, sclk_mmc<n> value was different for
various boards.

Setting the correct clock generation path should fix the issues
reported in above referenced commit. The changes committed during the
earlier patch has also been reverted here.
Reported-by: NDoug Anderson <dianders@chromium.org>
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
Tested-by: NDoug Anderson <dianders@chromium.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

As reported by Rob Herring[1] there were some mismatched types between
drivers/clk/ux500/clk.h and the corresponding function definitions:

drivers/clk/ux500/clk-prcc.c:145:13: error: conflicting types for 'clk_reg_prcc_pclk'
drivers/clk/ux500/clk-prcc.c:155:13: error: conflicting types for 'clk_reg_prcc_kclk'

[1] http://article.gmane.org/gmane.linux.ports.arm.kernel/232246Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: Rob Herring <robherring2@gmail.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>

The new common clock drivers for exynos are using compile
time constants and soc_is_exynos* macros to provide backwards
compatibility for pre-DT systems, which is not possible with
multiplatform kernels. This moves all the necessary
information back into platform code and removes the mach/*
header inclusions.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Cc: Mike Turquette <mturquette@linaro.org>

Factor out the SP810 clocking code into a separate driver,
selecting better (faster) parent at clk_prepare() time.
This is to avoid problems with clocking infrastructure
initialisation order, in particular to avoid dependency
of fixed clock being initialized before SP810. It also
makes vexpress platform OF-based clock initialisation code
unnecessary.
Signed-off-by: NPawel Moll <pawel.moll@arm.com>
Tested-by: NCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: add .unprepare, FIXME comment, cleaned up code]

Calling clk-si5351 driver non-OF ready was too early. This patch
makes clk-si5351 depend on CONFIG_OF again, until things get sorted out.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reported-by: NStephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed spelling of Stephen's name]

The common clock api provides some helpers for clk-providers but does
not export these helpers. This hinders clk-providers to be built as modules.
This patch adds __clk_get_flags() to the list of exported symbols.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

With this patch, the socfpga clk driver is able to query the clock and clock
rates appropriately.
Signed-off-by: NDinh Nguyen <dinguyen@altera.com>
Reviewed-by: NPavel Machek <pavel@denx.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The case of PLL_TYPE_WM8750 in both these functions is missing a break
statement causing a fall-through to the default: case.

Insert the missing break statements.
Signed-off-by: NTony Prisk <linux@prisktech.co.nz>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This commit uses the new fixed-rate support on the composite clock to
unify osc24M_fixed and osc24M clocks, so it matches the actual hardware.
Signed-off-by: NEmilio López <emilio@elopez.com.ar>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: replace clk_register_gatable_osc with a call to
clk_register_composite]

The composite clock assumes that any clock implementing the .recalc_rate
callback will also implement .round_rate and .set_rate.  This is not
always true; the basic fixed-rate clock will only implement .recalc_rate
and a fixed-divider clock may choose to implement .recalc_rate and
.round_rate but not .set_rate.

Fix this by conditionally registering .round_rate and .set_rate
callbacks based on the rate_ops passed in to clk_composite_register.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: NEmilio López <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>

Rename all div_hw and div_ops related variables and functions to use
rate_hw, rate_ops, etc.  This is to make the rate-change portion of the
composite clk implementation more generic.  A patch following this one
will allow for fixed-rate clocks to reuse this infrastructure.
Signed-off-by: NMike Turquette <mturquette@linaro.org>
Reviewed-by: NPrashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: NEmilio López <emilio@elopez.com.ar>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>

This patch adds a common clock driver for Silicon Labs Si5351a/b/c
i2c programmable clock generators. Currently, the driver does not
support VXCO feature of si5351b. Passing platform_data or DT bindings
selectively allows to overwrite stored Si5351 configuration which is
very helpful for clock generators with empty eeprom configuration.
Corresponding device tree binding documentation is also added.
Signed-off-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Tested-by: NDaniel Mack <zonque@gmail.com>
Acked-by: NGuenter Roeck <linux@roeck-us.net>
Tested-by: NMichal Bachraty <michal.bachraty@streamunlimited.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Add support for DT "fixed-factor-clock" binding to the common fixed
factor clock support.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: NChristian Ruppert <christian.ruppert@abilis.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Avoid to use cpu_is_xxx() in pxa gpio driver. Use platform_device_id
to identify the difference.
Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>

Notifiers may return NOTIFY_(OK|DONE|STOP|BAD). The CCF uses an
inconsistent mix of checking against NOTIFY_STOP or NOTIFY_BAD.
This inconsistency leaves errors undetected in some cases:
clk_set_parent() calls __clk_speculate_rates(), which stops when it
hits a NOTIFIER_BAD (STOP is ignored), and passes this value back to the
caller.
clk_set_parent() compares this return value against NOTIFY_STOP only,
ignoring NOTIFY_BAD returns.

Use NOTIFY_STOP_MASK to detect a negative notifier return value and
document all four return value options.
Signed-off-by: NSoren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The patch setups the first version of the clock tree for ab850x, which
is used by u8500 platforms. Mainly sysctrl clocks are used.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Tested-by: NFabio Baltieri <fabio.baltieri@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The abx500 sysctrl clocks are using the ab8500 sysctrl driver to
modify the clock hardware. Sysctrl clocks are represented by a
ab8500 sysctrl register and with a corresponding bitmask.

The sysctrl clocks are slow path clocks, which means clk_prepare
and clk_unprepare will be used to gate|ungate these clocks.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

cpu_freq_select is used as array subscript, thus the valid value range
is 0 ... ARRAY_SIZE() - 1.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed up trivial merge issues]

Updating the clock tree topology must be protected with the spinlock
when doing clk_set_parent, otherwise we can not handle the migration
of the enable_count in a safe manner.

While issuing the .set_parent callback to make the clk-hw perform the
switch to the new parent, we can not hold the spinlock since it is must
be allowed to be slow path. This complicates error handling, but is still
possible to achieve.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Fixup the broken feature of allowing reparent of a clk to the
orhpan list and vice verse. When operating on a single-parent
clk, the .set_parent callback for the clk hw is optional to
implement, but for a multi-parent clk it is mandatory.

Moreover improve the errorhandling by verifying the prerequisites
before triggering clk notifiers. This will prevent unnecessary
rollback with ABORT_RATE_CHANGE.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Split __clk_reparent into three pieces, one for doing the actual
reparent for updating the clock tree topology, one for the
COMMON_CLK_DEBUG code and one for doing the rate recalculation.

This patch also makes it possible to hold the spinlock over the
update of the clock tree topology, which could not be done before
when both debugfs updates and clock rate updates was done within
the same function.
Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

In legacy setup, sclk_mmc{0,1,2,3} used PRE_RATIO bit-field (8-bit wide)
instead of RATIO bit-field (4-bit wide) for dividing clock rate.

With current common clock setup, we are using RATIO bit-field which
is creating FIFO read errors while accessing eMMC. Changing over to
use PRE_RATIO bit-field fixes this issue.

dwmmc_exynos 12200000.dwmmc0: data FIFO error (status=00008020)
mmcblk0: error -5 transferring data, sector 1, nr 7, cmd response 0x900, card status 0x0
end_request: I/O error, dev mmcblk0, sector 1
Signed-off-by: NTushar Behera <tushar.behera@linaro.org>
CC: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This patch adds clock indexes for ACLK_DIV0, ACLK_DIV1,
ACLK_400_MCUISP, ACLK_MCUISP_DIV0, ACLK_MCUISP_DIV1,
DIVACLK_400_MCUISP and DIVACLK_200 so these clocks are
available to the consumers (Exynos4x12 FIMC-IS subsystem).
While at it, indentation of the mux clocks table is
corrected.
Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

Fixes the below compilation error during non-dt build.
drivers/clk/samsung/clk.c: In function 'samsung_clk_of_register_fixed_ext':
drivers/clk/samsung/clk.c:252:2: error: implicit declaration of function 'for_each_matching_node_and_match' [-Werror=implicit-function-declaration]
drivers/clk/samsung/clk.c:252:60: error: expected ';' before '{' token
Signed-off-by: NSachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>

This removes <mach/hardware.h> and <mach/db8500-regs.h>
from the Ux500, merging them into the local include
"db8500-regs.h" in mach-ux500. There is some impact
outside the ux500 machine, but most of it is dealt with
in earlier patches.

Contains portions of a clean-up patch from Arnd Bergmann.

Cc: Samuel Ortiz <sameo@linux.intel.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The ux500 clock driver was including <mach/db8500-regs.h>
which will not work when building for multiplatform support
since <mach/*> is going away.

Pass the base adresses in the init call instead.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Mike Turquette <mturquette@linaro.org>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NUlf Hansson <ulf.hansson@linaro.org>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

A gap exists in the binding's clock ID definitions. Fix the clock driver
to be consistent. This allows pclk to be looked up through device tree
and prevents:

ERROR: could not get clock /pmc:pclk(0)
Signed-off-by: NStephen Warren <swarren@nvidia.com>

The UART driver enables the console uart clock, so we don't need to do that
anymore in this file.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Implement clocks for Tegra114.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>

Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: NPeter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NStephen Warren <swarren@nvidia.com>