1. 04 9月, 2017 25 次提交
  2. 02 9月, 2017 1 次提交
  3. 30 8月, 2017 14 次提交
    • P
      clocksource: mips-gic-timer: Use new GIC accessor functions · e07127a0
      Paul Burton 提交于
      Switch from calling functions exported by the GIC interrupt controller
      to using new accessors provided by asm/mips-gic.h. This will allow the
      counter-handling functionality to be removed from the interrupt
      controller driver, where it doesn't really belong, and also allow for
      inlining of the accesses to the GIC.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Acked-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17021/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e07127a0
    • P
      MIPS: GIC: Introduce asm/mips-gic.h with accessor functions · 582e2b4a
      Paul Burton 提交于
      This patch introduces a new header providing accessor functions for the
      MIPS Global Interrupt Controller (GIC) mirroring those provided for the
      other 2 components of the MIPS Coherent Processing System (CPS) - the
      Coherence Manager (CM) & Cluster Power Controller (CPC).
      
      This header makes use of the new standardised CPS accessor macros where
      possible, but does require some custom accessors for cases where we have
      either a bit or a register per interrupt.
      
      A major advantage of this over the existing
      include/linux/irqchip/mips-gic.h definitions is that code performing
      accesses can become much simpler, for example this:
      
        gic_update_bits(GIC_REG(SHARED, GIC_SH_SET_TRIGGER) +
                        GIC_INTR_OFS(intr), 1ul << GIC_INTR_BIT(intr),
                        (unsigned long)trig << GIC_INTR_BIT(intr));
      
      ...can become simply:
      
        change_gic_trig(intr, trig);
      
      The accessors handle 32 vs 64 bit in the same way as for CM & CPC code,
      which means that GIC code will also not need to worry about the access
      size in most cases. They are also accessible outside of
      drivers/irqchip/irq-mips-gic.c which will allow for simplification in
      the use of the non-interrupt portions of the GIC (eg. counters) which
      currently require the interrupt controller driver to expose helper
      functions for access.
      
      This patch doesn't change any existing code over to use the new
      accessors yet, since a wholesale change would be invasive & difficult to
      review. Instead follow-on patches will convert code piecemeal to use
      this new header. The one change to existing code is to rename gic_base
      to mips_gic_base & make it global, in order to fit in with the naming
      expected by the standardised CPS accessor macros.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17020/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      582e2b4a
    • J
      irqchip: mips-gic: SYNC after enabling GIC region · a0ffec3d
      James Hogan 提交于
      A SYNC is required between enabling the GIC region and actually trying
      to use it, even if the first access is a read, otherwise its possible
      depending on the timing (and in my case depending on the precise
      alignment of certain kernel code) to hit CM bus errors on that first
      access.
      
      Add the SYNC straight after setting the GIC base.
      
      [paul.burton@imgtec.com:
        Changes later in this series increase our likelihood of hitting this
        by reducing the amount of code that runs between enabling the GIC &
        accessing it.]
      
      Fixes: a7057270 ("irqchip: mips-gic: Add device-tree support")
      Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Jason Cooper <jason@lakedaemon.net>
      Cc: James Hogan <james.hogan@imgtec.com>
      Cc: linux-kernel@vger.kernel.org
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17019/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a0ffec3d
    • C
      MIPS: Don't use dma_cache_sync to implement fd_cacheflush · 1dd71588
      Christoph Hellwig 提交于
      The floppy drivers doesn't otherwise use the DMA API, so indirecting
      through it just for cache flushing in MIPS-specific code just call
      dma_cache_wback_inv directly.
      Signed-off-by: NChristoph Hellwig <hch@lst.de>
      Cc: iommu@lists.linux-foundation.org
      Cc: Marek Szyprowski <m.szyprowski@samsung.com>
      Cc: Robin Murphy <robin.murphy@arm.com>
      Cc: Michal Simek <monstr@monstr.eu>
      Cc: David Howells <dhowells@redhat.com>
      Cc: Guan Xuetao <gxt@mprc.pku.edu.cn>
      Cc: Chris Zankel <chris@zankel.net>
      Cc: Max Filippov <jcmvbkbc@gmail.com>
      Cc: x86@kernel.org
      Cc: linux-mips@linux-mips.org
      Cc: linux-ia64@vger.kernel.org
      Cc: linuxppc-dev@lists.ozlabs.org
      Cc: linux-xtensa@linux-xtensa.org
      Cc: linux-sh@vger.kernel.org
      Cc: linux-kernel@vger.kernel.org
      Patchwork: https://patchwork.linux-mips.org/patch/17183/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1dd71588
    • P
      MIPS: generic: Bump default NR_CPUS to 16 · c2c03291
      Paul Burton 提交于
      In generic_defconfig set CONFIG_NR_CPUS to 16 rather than 2, which is a
      rather too low limit for many modern day MIPS systems.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16949/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c2c03291
    • P
      MIPS: generic: Don't explicitly disable CONFIG_USB_SUPPORT · f8bfffc1
      Paul Burton 提交于
      Leave CONFIG_USB_SUPPORT at its default, allowing board config fragments
      to make use of USB drivers without needing to override it & trigger
      warnings from merge_config.sh.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16948/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      f8bfffc1
    • P
      MIPS: Make CONFIG_MIPS_MT_SMP default y · 5cbf9688
      Paul Burton 提交于
      On systems that support MT ASE multithreading (ie. VPEs) we are very
      likely to want to include that support as default. Rather than setting
      it in various defconfigs, simply make CONFIG_MIPS_MT_SMP default y such
      that systems which select CONFIG_SYS_SUPPORTS_MULTITHREADING get it by
      default.
      
      As well as allowing us to remove the selection of CONFIG_MIPS_MT_SMP
      from various defconfigs, this also allows the generated generic
      defconfigs which derive from generic_defconfig to automatically gain
      support for MT ASE SMP when building for a suitable (pre-MIPSr6) ISA.
      
      For malta_kvm_guest_defconfig CONFIG_MIPS_MT_SMP is explicitly disabled
      since enabling SMP implicitly disables CONFIG_KVM_GUEST, which depends
      on CONFIG_BROKEN_ON_SMP.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16947/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      5cbf9688
    • P
      MIPS: Prevent direct use of generic_defconfig · a4c2f797
      Paul Burton 提交于
      Using generic_defconfig directly is unlikely to be what a user actually
      wants to do - it doesn't specify any particular ISA revision & it
      doesn't enable any board or driver support, resulting in a largely
      useless kernel.
      
      Prevent users from using it directly, printing a helpful message to
      point them in the right direction if they attempt to.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16946/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      a4c2f797
    • P
      MIPS: NI 169445: Only include in 32r2el kernels · 9e111ee7
      Paul Burton 提交于
      The NI 169445 board uses a little endian MIPS32r2 CPU, and therefore
      including board support in kernels that are unable to run on such a CPU
      is pointless.
      
      Specify requirements in the board config fragment that cause the NI
      169445 board support to only be included in generic kernels that target
      little endian MIPS32r2 CPUs.
      
      For example, NI 169445 support will be included when configuring using
      32r2el_defconfig but not when using 64r6_defconfig.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Acked-by: NNathan Sullivan <nathan.sullivan@ni.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16945/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      9e111ee7
    • P
      MIPS: SEAD-3: Only include in 32 bit kernels by default · c7a1d3d8
      Paul Burton 提交于
      The MIPS SEAD-3 development board has only ever been used with 32 bit
      CPUs, so including support for it in 64 bit kernels is wasteful since
      those kernels will never run on a SEAD-3.
      
      Specify a requirement in the SEAD-3 board config fragment that ensures
      the board support is only included in 32 bit kernels, by checking that
      CONFIG_32BIT=y.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16944/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      c7a1d3d8
    • P
      MIPS: generic: Allow filtering enabled boards by requirements · 27e0d4b0
      Paul Burton 提交于
      Up until now when configuring a generic kernel all board config
      fragments have been merged by default unless boards are explicitly
      selected by the user specifying BOARDS=.
      
      In many cases this is sub-optimal, since some boards don't make sense to
      include in some kernels. For example the MIPS SEAD-3 development board
      has only ever been used with 32 bit CPUs, so including support for the
      SEAD-3 in a 64 bit kernel is wasteful.
      
      This patch introduces support for specifying requirements in board
      config fragments, using comments formatted like so:
      
        # require CONFIG_BLA=y
      
      For example the SEAD-3 board could specify that it should only be merged
      for 32 bit kernels using a requirement line like the following:
      
        # require CONFIG_32BIT=y
      
      A new generic-board-config.sh script is introduced to handle selecting
      the board config fragments to merge & calling merge_config.sh to merge
      them. In order to allow requirements to check Kconfig symbols that are
      implicitly selected, rather than explicitly specified by
      generic_defconfig or one of the ISA config fragments, an intermediate
      .config file is saved & used as a reference when checking requirements.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/16943/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      27e0d4b0
    • P
      MIPS: CPS: Detect CPUs in secondary clusters · 1ec9dd80
      Paul Burton 提交于
      As a first step towards supporting multi-cluster systems, detect cores &
      VPs in secondary clusters & record their cluster information in the
      cpu_data array. The "VP topology" line printed during boot is extended
      to display multiple clusters. On a single cluster it shows output like
      the following:
      
        VP topology: {4,4}
      
      This would indicate a system with 2 cores which each contain 4 VPs. We
      extend this to cover multiple clusters in a natural way:
      
        VP topology: {4,4},{2,2}
      
      This would indicate a system with 2 clusters. The first cluster contains
      2 cores which each contain 4 VPs. The second cluster contains 2 cores
      which each contain 2 VPs.
      
      Actually booting these cores & VPs is left to further patches once other
      pieces are in place.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17017/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      1ec9dd80
    • P
      MIPS: CPS: Cluster support for topology functions · 3c9b4166
      Paul Burton 提交于
      Modify the functions we use to read information about the topology of
      the system (the number of cores, VPs & IOCUs that it contains) in order
      to take into account multiple clusters, and provide a new function to
      determine the number of clusters in the system.
      
      Users of these functions are modified only such that they continue to
      build successfully - having them actually handle multiple clusters is
      left to further patches.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17016/
      Patchwork: https://patchwork.linux-mips.org/patch/17218/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      3c9b4166
    • P
      MIPS: CPS: Have asm/mips-cps.h include CM & CPC headers · e83f7e02
      Paul Burton 提交于
      With Coherence Manager (CM) 3.5 information about the topology of the
      system, which has previously only been available through & accessed from
      the CM, is now also provided by the Cluster Power Controller (CPC). This
      includes a new CPC_CONFIG register mirroring GCR_CONFIG, and similarly a
      new CPC_Cx_CONFIG register mirroring GCR_Cx_CONFIG.
      
      In preparation for adjusting functions such as mips_cm_numcores(), which
      have previously only needed to access the CM, to also access the CPC
      this patch modifies the way we use the various CPS headers. Rather than
      having users include asm/mips-cm.h or asm/mips-cpc.h individually we
      instead have users include asm/mips-cps.h which in turn includes
      asm/mips-cm.h & asm/mips-cpc.h. This means that users will gain access
      to both CM & CPC registers by including one header, and most importantly
      it makes asm/mips-cps.h an ideal location for helper functions which
      need to access the various components of the CPS.
      Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/17015/
      Patchwork: https://patchwork.linux-mips.org/patch/17217/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e83f7e02