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  1. 17 12月, 2009 1 次提交
    • D
      MIPS: Put PGD in C0_CONTEXT for 64-bit R2 processors. · 82622284
      David Daney 提交于
      Processors that support the mips64r2 ISA can in four instructions
      convert a shifted PGD pointer stored in the upper bits of c0_context
      into a usable pointer.  By doing this we save a memory load and
      associated potential cache miss in the TLB exception handlers.
      
      Since the upper bits of c0_context were holding the CPU number, we
      move this to the upper bits of c0_xcontext which doesn't have enough
      bits to hold the PGD pointer, but has plenty for the CPU number.
      Signed-off-by: NDavid Daney <ddaney@caviumnetworks.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      82622284
  2. 02 11月, 2009 1 次提交
    • K
      MIPS: Fix machine check exception in kmap_coherent() · 0f334a3e
      Kevin Cernekee 提交于
      On an SMP system with cache aliases, the following sequence of events may
      happen:
      
      1) copy_user_highpage() runs on CPU0, invoking kmap_coherent() to create a
         temporary mapping in the fixmap region
      2) copy_page() starts on CPU0
      3) CPU1 sends CPU0 an IPI asking CPU0 to run local_r4k_flush_cache_page()
      4) CPU0 takes the interrupt, interrupting copy_page()
      5) local_r4k_flush_cache_page() on CPU0 calls kmap_coherent() again
      6) The second invocation of kmap_coherent() on CPU0 tries to use the
         same fixmap virtual address that was being used by copy_user_highpage()
      7) CPU0 throws a machine check exception for the TLB address conflict
      
      Fixed by creating an extra set of fixmap entries for use in interrupt
      handlers.  This prevents fixmap VA conflicts between copy_user_highpage()
      running in user context, and local_r4k_flush_cache_page() invoked from an
      SMP IPI.
      Signed-off-by: NKevin Cernekee <cernekee@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      0f334a3e
  3. 23 9月, 2009 3 次提交
  4. 22 9月, 2009 1 次提交
  5. 18 9月, 2009 1 次提交
    • W
      MIPS: Shrink the size of tlb handler · e0cc87f5
      Wu Fei 提交于
      By combining swapper_pg_dir and module_pg_dir, several if conditions
      can be eliminated from the tlb exception handler. The reason they
      can be combined is that, the effective virtual address of vmalloc
      returned is at the bottom, and of module_alloc returned is at the
      top. It also fixes the bug in vmalloc(), which happens when its
      return address is not covered by the first pgd.
      Signed-off-by: NWu Fei <at.wufei@gmail.com>
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      e0cc87f5
  6. 25 6月, 2009 1 次提交
  7. 14 5月, 2009 1 次提交
    • R
      MIPS: Fix highmem. · bb86bf28
      Ralf Baechle 提交于
      Commit 35133692 (kernel.org) rsp.
      b3594a089f1c17ff919f8f78505c3f20e1f6f8ce (linux-mips.org):
      
      > From: Chris Dearman <chris@mips.com>
      > Date: Wed, 19 Sep 2007 00:58:24 +0100
      > Subject: [PATCH] [MIPS] Allow setting of the cache attribute at run time.
      >
      > Slightly tacky, but there is a precedent in the sparc archirecture code.
      
      introduces the variable _page_cachable_default, which defaults to zero and.
      is used to create the prototype PTE for __kmap_atomic in
      arch/mips/mm/init.c:kmap_init before initialization in
      arch/mips/mm/c-r4k.c:coherency_setup, so the default value of 0 will be
      used as the CCA of kmap atomic pages which on many processors is not a
      defined CCA value and may result in writes to kmap_atomic pages getting
      corrupted.  Debugged by Jon Fraser (jfraser@broadcom.com).
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      bb86bf28
  8. 30 3月, 2009 1 次提交
  9. 16 6月, 2008 1 次提交
  10. 29 4月, 2008 5 次提交
  11. 20 2月, 2008 1 次提交
  12. 27 11月, 2007 1 次提交
    • R
      [MIPS] 64-bit Sibyte kernels need DMA32. · cce335ae
      Ralf Baechle 提交于
      Sibyte SOCs only have 32-bit PCI.  Due to the sparse use of the address
      space only the first 1GB of memory is mapped at physical addresses
      below 1GB.  If a system has more than 1GB of memory 32-bit DMA will
      not be able to reach all of it.
      
      For now this patch is good enough to keep Sibyte users happy but it seems
      eventually something like swiotlb will be needed for Sibyte.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      cce335ae
  13. 16 11月, 2007 1 次提交
  14. 17 10月, 2007 1 次提交
    • R
      [MIPS] Fix aliasing bug in copy_user_highpage, take 2. · 985c30ef
      Ralf Baechle 提交于
      Turns out b868868a  wasn't quite right.
      When called for a page that isn't marked dirty it would artificially
      create an alias instead of doing the obvious thing and access the page
      via KSEG0.
      
      The same issue also exists in copy_to_user_page and copy_from_user_page
      which was causing the machine to die under rare circumstances for example
      when running ps if the BUG_ON() assertion added by the earlier fix was
      getting triggered.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      985c30ef
  15. 12 9月, 2007 1 次提交
    • R
      [MIPS] Fix aliasing bug in copy_user_highpage. · b868868a
      Ralf Baechle 提交于
      Copy_user_highpage was written assuming it was only being called for
      breaking COW pages in which case the source page isn't cached as in
      marked cachable under it kernel virtual address.  If it is called anyway
      the aliasing avoidance strategy implemented by kmap_coherent will fail.
      Avoid the use of kmap_coherent for pages marked dirty and to avoid
      another instance of this sort of bug, place a BUG_ON in kmap_coherent.
      Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
      b868868a
  16. 27 8月, 2007 1 次提交
  17. 24 7月, 2007 1 次提交
  18. 11 5月, 2007 1 次提交
  19. 27 4月, 2007 2 次提交
  20. 25 3月, 2007 2 次提交
  21. 20 2月, 2007 1 次提交
  22. 19 2月, 2007 1 次提交
  23. 07 2月, 2007 3 次提交
  24. 25 1月, 2007 1 次提交
  25. 14 12月, 2006 1 次提交
  26. 12 12月, 2006 1 次提交
  27. 30 11月, 2006 3 次提交
  28. 22 10月, 2006 1 次提交