- 14 12月, 2011 2 次提交
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由 Andrew Lunn 提交于
Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NMichael Walle <michael@walle.cc> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Andrew Lunn 提交于
Move the *_mbus_dram_info structure into the orion platform and call it orion_mbus_dram_info everywhere. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Tested-by: NMichael Walle <michael@walle.cc> Acked-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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- 17 5月, 2011 6 次提交
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由 Andrew Lunn 提交于
Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Andrew Lunn 提交于
Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Andrew Lunn 提交于
Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Andrew Lunn 提交于
Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Andrew Lunn 提交于
Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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由 Andrew Lunn 提交于
Changing eg 0xffffffff to DMA_BIT_MASK(32) etc allows easier side by side comparision of identical code which can be consolidated. Signed-off-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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- 04 3月, 2011 1 次提交
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由 Lennert Buytenhek 提交于
This patch makes the various mach dirs that use the plat-orion time code pass in timer and bridge addresses explicitly, instead of having plat-orion get those values by including a mach dir include file -- the latter mechanism is problematic if you want to support multiple ARM platforms in the same kernel image. Signed-off-by: NLennert Buytenhek <buytenh@secretlab.ca> Signed-off-by: NNicolas Pitre <nico@fluxnic.net>
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- 06 11月, 2009 1 次提交
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由 Lennert Buytenhek 提交于
Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 23 5月, 2009 1 次提交
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由 Nicolas Pitre 提交于
Since commit eb0519b5, mv643xx_eth is non functional on ARM because the platform device declaration does not include any coherent DMA mask and coherent memory allocations fail. Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 22 5月, 2009 1 次提交
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由 Martin Michlmayr 提交于
Remove explicit names from platform device resources since they will automatically be named after the platform device they're associated with. Signed-off-by: NMartin Michlmayr <tbm@cyrius.com> Acked-by: NRussell King <linux@arm.linux.org.uk> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 24 4月, 2009 1 次提交
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由 Nicolas Pitre 提交于
Symbols like SOFT_RESET are way too generic to be exported at large. To avoid this, let's move the mbus bridge register defines into a separate file and include it where needed. This affects mach-kirkwood, mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all share code in plat-orion which relies on those defines. Some other defines have been moved to narrower scopes, or simply deleted when they had no user. This fixes compilation problem with mpt2sas on the above listed platforms. Signed-off-by: NNicolas Pitre <nico@marvell.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 04 3月, 2009 1 次提交
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由 Riku Voipio 提交于
All the pieces were ready, just matter of assembling them together. Signed-off-by: NRiku Voipio <riku.voipio@iki.fi> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 20 2月, 2009 2 次提交
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由 Lennert Buytenhek 提交于
On pre-A0 revisions of the mv78xx0 SoC, the third and fourth ethernet interface are not brought out to pins, but are internally cross-connected, so if we run on pre-A0 silicon, we'll force eth2 and eth3 to PHYless mode. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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由 Lennert Buytenhek 提交于
During boot, identify which chip stepping we're running on (determined by looking at the first PCIe unit's device ID and revision registers), and print a message with the details about what we found. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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- 04 12月, 2008 1 次提交
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由 Ronen Shitrit 提交于
The Orion ehci driver serves the Orion, kirkwood and DD Soc families. Since each of those integrate a different USB phy we should have the ability to use few initialization sequences or to leave the boot loader phy settings as is. Signed-off-by: NRonen Shitrit <rshitrit@marvell.com>
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- 26 9月, 2008 1 次提交
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由 Lennert Buytenhek 提交于
Wire up the ethernet port's error interrupt so that the mv643xx_eth driver can sleep for SMI event completion instead of having to busy-wait for it. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com> Signed-off-by: NNicolas Pitre <nico@marvell.com>
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- 05 9月, 2008 1 次提交
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由 Lennert Buytenhek 提交于
Which top-level unit's SMI interface to use should be a property of the top-level unit, not of the individual ports. This patch moves the ->shared_smi pointer from the per-port platform data to the global platform data. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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- 09 8月, 2008 1 次提交
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由 Lennert Buytenhek 提交于
This patch performs the equivalent include directory shuffle for plat-orion, and fixes up all users. Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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- 07 8月, 2008 1 次提交
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由 Russell King 提交于
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 23 6月, 2008 1 次提交
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由 Stanislav Samsonov 提交于
The Marvell Discovery Duo (MV78xx0) is a family of ARM SoCs featuring (depending on the model) one or two Feroceon CPU cores with 512K of L2 cache and VFP coprocessors running at (depending on the model) between 800 MHz and 1.2 GHz, and features a DDR2 controller, two PCIe interfaces that can each run either in x4 or quad x1 mode, three USB 2.0 interfaces, two 3Gb/s SATA II interfaces, a SPI interface, two TWSI interfaces, a crypto accelerator, IDMA/XOR engines, a SPI interface, four UARTs, and depending on the model, two or four gigabit ethernet interfaces. This patch adds basic support for the platform, and allows booting on the MV78x00 development board, with functional UARTs, SATA, PCIe, GigE and USB ports. Signed-off-by: NStanislav Samsonov <samsonov@marvell.com> Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
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