This enables us to have a default device tree per SoC family to be built
into the kernel. The default device tree for XLP3xx has been added as part
of this change. Later this can be used to provide support default boards
for XLP2xx and XLP9xx SoCs.

Kconfig options are provided for each default device tree so that just the
needed ones can be selected to be built into the kernel.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5023/Acked-by: NJohn Crispin <blogic@openwrt.org>

On XLR/XLS, the cpu cores communicate with fast on-chip devices
(e.g. network accelerator, security engine etc.) using the Fast
Messaging Network(FMN). The FMN queues and credits needs to be
configured and intialized before it can be used.

The co-processor 2 on XLR/XLS CPU cores has registers for FMN access,
and the XLR/XLS has custom instructions for sending and loading
messages.  The FMN can deliver also per-cpu interrupts when messages
are available at the CPU.

This patch adds FMN initialization, adds interrupt setup and handling,
and also provides support for sending and receiving FMN messages.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4468Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Upto 4 Netlogic XLP SoCs can be connected over ICI links to form a
coherent multi-node system.  Each SoC has its own set of on-chip
devices including PIC.  To support this, add a per SoC stucture and
use it for the PIC and SYS block addresses instead of using global
variables.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4469Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Initial code to support more than 32 cpus. The platform CPU mask
is updated from 32-bit mask to cpumask_t. Convert places that use
cpu_/cpus_ functions to use cpumask_* functions.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4464Signed-off-by: NJohn Crispin <blogic@openwrt.org>

At this point early printk is available, so debugging device tree
issues is easier.
Signed-off-by: NJayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4460Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Provide a config option to embed a device tree for XLP evaluation
boards. This DTB will be used if the firmware does not pass in a
device tree pointer.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Patchwork: http://patchwork.linux-mips.org/patch/4103/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Move the function device_tree_init() from netlogic/xlp/of.c
to setup.c, and remove the wrapper functions reserve_mem_mach()
and free_mem_mach().

Remove file netlogic/xlp/of.c, and the Makefile entry for it.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Patchwork: http://patchwork.linux-mips.org/patch/4097/Signed-off-by: NJohn Crispin <blogic@openwrt.org>

Probe and add devices on SoC "simple-bus" on startup. This will
in turn add devices like I2C controller that are specified in the
device tree under 'soc'.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3762/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Starting other threads in the core will change the number of
TLB entries of a CPU.  Re-calculate current_cpu_data.tlbsize
on the boot cpu after enabling and waking up other threads.

The secondary CPUs do not need this logic because the threads
are enabled on the secondary cores at wakeup and before cpu_probe.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3751/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Create a common NMI and reset handler in smpboot.S and use this for
both XLR and XLP.  In the earlier code, the woken up CPUs would
busy wait until released, switch this to wakeup by NMI.

The initial wakeup code or XLR and XLP are differ since they are
started from different bootloaders (XLP from u-boot and XLR from
netlogic bootloader). But in both platforms the woken up CPUs wait
and are released by sending an NMI.

Add support for starting XLR and XLP in 1/2/4 threads per core.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2970/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Update common files to support XLP.
- Add arch/mips/include/asm/netlogic/xlp-hal for register definitions
  and access macros
- Add arch/mips/netlogic/xlp/ for XLP specific files.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2967/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

- Move code that can be shared with XLP (irq.c, smp.c, time.c and
  xlr_console.c) to arch/mips/netlogic/common
- Add asm/netlogic/haldefs.h and asm/netlogic/common.h for common and
  io functions shared with XLP
- remove type 'nlm_reg_t *' and use uint64_t for mmio offsets
- Move XLR specific code in smp.c to xlr/wakeup.c
- Move XLR specific PCI code from irq.c to mips/pci/pci-xlr.c
- Provide API for pic functions called from common/irq.c
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2964/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

* include/asm/netlogic added with files common for all Netlogic processors
  (common with XLP which will be added later)
* include/asm/netlogic/xlr for XLR/XLS chip specific files
* netlogic/xlr for XLR/XLS platform files
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
To: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/2334/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>