- 29 9月, 2015 1 次提交
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由 Aravind Gopalakrishnan 提交于
The scrub rate control register has moved to function 2 in PCI config space and is at a different offset on family 0x15, models 0x60 and later. The minimum recommended scrub rate has also changed. (Refer to D18F2x1c9_dct[1:0][DramScrub] in Fam15hM60h BKDG). Adjust set_scrub_rate() and get_scrub_rate() functions to accommodate this. Tested on F15hM60h, Fam15h, models 00h-0fh and Fam10h systems. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1443440593-2316-2-git-send-email-Aravind.Gopalakrishnan@amd.com [ Cleanup conditionals. ] Signed-off-by: NBorislav Petkov <bp@suse.de>
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- 28 9月, 2015 1 次提交
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由 Toshi Kani 提交于
Updating dimm_label to an empty string does not make much sense. Change the sysfs dimm_label store operation to fail a request when an input string is empty. Suggested-by: NBorislav Petkov <bp@alien8.de> Signed-off-by: NToshi Kani <toshi.kani@hpe.com> Cc: elliott@hpe.com Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1443124767.25474.172.camel@hpe.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 26 9月, 2015 2 次提交
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由 Toshi Kani 提交于
Sysfs "dimm_label" and "chX_dimm_label" nodes have the following issues in their store operation: 1) A newline-terminated input string causes redundant newlines: # echo "test" > /sys/bus/mc0/devices/dimm0/dimm_label # cat /sys/bus/mc0/devices/dimm0/dimm_label test # od -bc /sys/bus/mc0/devices/dimm0/dimm_label 0000000 164 145 163 164 012 012 t e s t \n \n 0000006 2) The original label string (31 characters) cannot be stored due to an improper size check: # echo "CPU_SrcID#0_Ha#0_Chan#0_DIMM#0" > /sys/bus/mc0/devices/dimm0/dimm_label # cat /sys/bus/mc0/devices/dimm0/dimm_label # od -bc /sys/bus/mc0/devices/dimm0/dimm_label 0000000 012 012 \n \n 0000002 3) An input string longer than the buffer size results a wrong label info as it allows a retry with the remaining string: # echo "CPU_SrcID#0_Ha#0_Chan#0_DIMM#0_TEST" > /sys/bus/mc0/devices/dimm0/dimm_label # cat /sys/bus/mc0/devices/dimm0/dimm_label _TEST Fix these issues by making the following changes: 1) Replace a newline character at the end by setting a null. It also assures that the string is null-terminated in the label buffer. 2) Check the label buffer size with 'sizeof(dimm->label)'. 3) Fail a request if its string exceeds the label buffer size. Signed-off-by: NToshi Kani <toshi.kani@hpe.com> Acked-by: NTony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Robert Elliott <elliott@hpe.com> Link: http://lkml.kernel.org/r/1443121564.25474.160.camel@hpe.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Toshi Kani 提交于
After 7d375bff ("sb_edac: Fix support for systems with two home agents per socket") sysfs "dimm_label" and "chX_dimm_label" show their label string without a newline "\n" at the end. [root@orange ~]# cat /sys/bus/mc0/devices/dimm0/dimm_label CPU_SrcID#0_Ha#0_Chan#0_DIMM#0[root@orange ~]# [root@orange ~]# cat /sys/devices/system/edac/mc/mc0/csrow0/ch0_dimm_label CPU_SrcID#0_Ha#0_Chan#0_DIMM#0[root@orange ~]# The label strings now have 31 characters, which are the same as EDAC_MC_LABEL_LEN. Since the snprintf()s in channel_dimm_label_show() and dimmdev_label_show() limit the whole length by EDAC_MC_LABEL_LEN, the newline in the format "%s\n" is ignored. [root@orange ~]# od -bc /sys/bus/mc0/devices/dimm0/dimm_label 0000000 103 120 125 137 123 162 143 111 104 043 060 137 110 141 043 060 C P U _ S r c I D # 0 _ H a # 0 0000020 137 103 150 141 156 043 060 137 104 111 115 115 043 060 000 _ C h a n # 0 _ D I M M # 0 \0 0000037 Fix it by using 'sizeof(dimm->label) + 1' as the whole length in the snprintf()s in channel_dimm_label_show() and dimmdev_label_show(). Reported-by: NRobert Elliott <elliott@hpe.com> Signed-off-by: NToshi Kani <toshi.kani@hpe.com> Acked-by: NTony Luck <tony.luck@intel.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Link: http://lkml.kernel.org/r/1442933883-21587-2-git-send-email-toshi.kani@hpe.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 25 9月, 2015 4 次提交
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由 Loc Ho 提交于
Add support for the SoC component. Signed-off-by: NLoc Ho <lho@apm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mark.rutland@arm.com Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1443055261-8613-4-git-send-email-lho@apm.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Loc Ho 提交于
Replace sprintf() with snprintf() to avoid possible string array overflow. Signed-off-by: NLoc Ho <lho@apm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mark.rutland@arm.com Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1443116287-11752-1-git-send-email-lho@apm.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Loc Ho 提交于
Add EDAC support for the L3 component. Signed-off-by: NLoc Ho <lho@apm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: ijc+devicetree@hellion.org.uk Cc: jcm@redhat.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mark.rutland@arm.com Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: patches@apm.com Cc: robh+dt@kernel.org Link: http://lkml.kernel.org/r/1443055261-8613-3-git-send-email-lho@apm.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Seth Jennings 提交于
In commit 7d375bff ("sb_edac: Fix support for systems with two home agents per socket") NUM_CHANNELS was changed to 8 and the channel space was renumerated to handle EN, EP, and EX configurations. The *_mci_bind_devs() functions - except for sbridge_mci_bind_devs() - got a new device presence check in the form of saw_chan_mask. However, sbridge_mci_bind_devs() still uses the NUM_CHANNELS for loop. With the increase in NUM_CHANNELS, this loop fails at index 4 since SB only has 4 TADs. This results in the following error on SB machines: EDAC sbridge: Some needed devices are missing EDAC sbridge: Couldn't find mci handler EDAC sbridge: Couldn't find mci handle This patch adapts the saw_chan_mask logic for sbridge_mci_bind_devs() as well. After this patch: EDAC MC0: Giving out device to module sbridge_edac.c controller Sandy Bridge Socket#0: DEV 0000:3f:0e.0 (POLLED) EDAC MC1: Giving out device to module sbridge_edac.c controller Sandy Bridge Socket#1: DEV 0000:7f:0e.0 (POLLED) Signed-off-by: NSeth Jennings <sjenning@redhat.com> Acked-by: NAristeu Rozanski <aris@redhat.com> Acked-by: NTony Luck <tony.luck@intel.com> Tested-by: NBorislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> # v4.2 Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1438798561-10180-1-git-send-email-sjenning@redhat.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 23 9月, 2015 5 次提交
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由 Aravind Gopalakrishnan 提交于
We already have edac_mem_types[] that enumerates the different kinds of memory. So, use that and remove the redundant memory_type[] array here. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1442436811-23382-2-git-send-email-Aravind.Gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Borislav Petkov 提交于
Drop CONFIG_EDAC_DEBUG ifdeffery too, while at it. Tested-by: NLoc Ho <lho@apm.com> Cc: linux-edac@vger.kernel.org Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Borislav Petkov 提交于
This driver creates its debugfs hierarchy under the toplevel debugfs dir - see i5100_init() - so make it use edac_debugfs_create_dir_at( , NULL) because we're not breaking userspace. Oh well. Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Borislav Petkov 提交于
Use the EDAC-specific wrappers. Drop CONFIG_EDAC_DEBUG ifdeffery. Cc: Thor Thayer <tthayer@opensource.altera.com> Cc: <linux-edac@vger.kernel.org> Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Borislav Petkov 提交于
Later patches will convert EDAC users to those. Signed-off-by: NBorislav Petkov <bp@suse.de>
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- 22 9月, 2015 1 次提交
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由 Borislav Petkov 提交于
... into a separate compilation unit and drop a couple of CONFIG_EDAC_DEBUG ifdefferies. Rename edac_create_debug_nodes() to edac_create_debugfs_nodes(), while at it. No functionality change. Cc: <linux-edac@vger.kernel.org> Signed-off-by: NBorislav Petkov <bp@suse.de>
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- 09 9月, 2015 2 次提交
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由 Aristeu Rozanski 提交于
dimm_dev_type has been incorrectly determined in sb_edac. This patch fixes it for Ivy Bridge and Haswell only since nothing like exists for Sandy Bridge. We tested this patch in multiple systems matching the results with the installed memory modules. Acked-by: NTony Luck <tony.luck@intel.com> Signed-off-by: NAristeu Rozanski <aris@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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由 Aristeu Rozanski 提交于
In case the memory banks are populated so the first channel isn't used, the DDRIO PCI device won't be visible and it won't be possible to determine the memory type. Acked-by: NTony Luck <tony.luck@intel.com> Signed-off-by: NAristeu Rozanski <aris@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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- 13 8月, 2015 4 次提交
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由 Borislav Petkov 提交于
This is an x86-specific module and would benefit from being closer to the arch code. Move it there. Update copyright while at it. Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Tony Luck <tony.luck@intel.com> Link: http://lkml.kernel.org/r/1439396985-12812-14-git-send-email-bp@alien8.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
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由 Borislav Petkov 提交于
This used to flush out MCEs logged during early boot and which were in the MCA registers from a previous system run. No need for that now, since we've moved to a genpool. Suggested-by: NTony Luck <tony.luck@intel.com> Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1439396985-12812-7-git-send-email-bp@alien8.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
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由 Chen, Gong 提交于
Use unified genpool to save Action Optional error events and put Action Optional error handling in the same notification chain as MCE error decoding. Signed-off-by: NChen, Gong <gong.chen@linux.intel.com> [ Fold in subsequent patch from Boris for early boot logging. ] Signed-off-by: NTony Luck <tony.luck@intel.com> [ Correct a lot. ] Signed-off-by: NBorislav Petkov <bp@suse.de> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/1439396985-12812-5-git-send-email-bp@alien8.deSigned-off-by: NIngo Molnar <mingo@kernel.org>
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由 Michael Walle 提交于
The commit de3910eb ("edac: change the mem allocation scheme to make Documentation/kobject.txt happy") changed the memory allocation for the csrows member. But ppc4xx_edac was forgotten in the patch. Fix it. Signed-off-by: NMichael Walle <michael@walle.cc> Cc: <stable@vger.kernel.org> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Link: http://lkml.kernel.org/r/1437469253-8611-1-git-send-email-michael@walle.ccSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 14 7月, 2015 1 次提交
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由 Aravind Gopalakrishnan 提交于
Currently, when decoding an MCE, we display 'CE' for a Deferred error, like this: [Hardware Error]: CPU:0 (15:2:0) MC4_STATUS[Over|CE|MiscV|-|AddrV|Deferred|-|UECC]: 0xdc04b00095080813 When the 'UC' bit in the MCx_STATUS register is clear, the error status is either a Corrected error or Deferred error as determined by the 'Deferred' bit. So do not print 'CE' on a deferred error. Refer to AMD Error Scope Hierarchy table in a newer BKDG (example: 49125_15h_Models_30h-3Fh_BKDG.pdf, section "RAS Features"). Signed-off-by: NAravind Gopalakrishnan <aravind.gopalakrishnan@amd.com> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/1436788382-6463-1-git-send-email-aravind.gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 10 7月, 2015 1 次提交
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由 Krzysztof Kozlowski 提交于
platform_driver does not need to set an owner because platform_driver_register() will set it. Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: Loc Ho <lho@apm.com> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Link: http://lkml.kernel.org/r/1436507243-11159-1-git-send-email-k.kozlowski@samsung.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 02 7月, 2015 1 次提交
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由 Aaro Koskinen 提交于
Commit debe6a62 ("MIPS: OCTEON: Update octeon-model.h code for new SoCs.") renamed some SoC model helper functions, but forgot to update the EDAC drivers resulting in build failures. Fix that. Cc: stable@vger.kernel.org # v4.0+ Signed-off-by: NAaro Koskinen <aaro.koskinen@nokia.com> Acked-by: NDavid Daney <david.daney@cavium.com> Cc: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: linux-mips@linux-mips.org Link: http://lkml.kernel.org/r/1435747132-10954-1-git-send-email-aaro.koskinen@nokia.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 25 6月, 2015 9 次提交
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由 Borislav Petkov 提交于
When during injection we populate MCi_MISC by writing into misc, we need to set the MiscV bit in the corresponding MCi_STATUS register which denotes that there's valid info in the MCi_MISC register. Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Borislav Petkov 提交于
We do get_online_cpus() and then start noodling with the bits. Do that *before* we grab the hotplug lock. Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Borislav Petkov 提交于
Save us an indentation level, widen to 80 cols, make the text more succinct and slender. Use i as the bank variable, same as what the documentation uses. Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Alan Tull 提交于
Suspend-to-RAM and EDAC support are mutually exclusive on SOCFPGA. If EDAC is enabled, it will prevent the platform from going into suspend. The reason is that the IRQ vectors for OCRAM reside on DDR and in Suspend-to-RAM mode we're executing out of OCRAM. If an ECC error occurs, we can't handle it so it was decided to make them mutually exclusive. Signed-off-by: NAlan Tull <atull@opensource.altera.com> Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com> Cc: dinh.linux@gmail.com Cc: dougthompson@xmission.com Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Cc: tthayer@opensource.altera.com Link: http://lkml.kernel.org/r/1433512155-9906-1-git-send-email-dinguyen@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 kbuild test robot 提交于
It is used there only anyway. Signed-off-by: NFengguang Wu <fengguang.wu@intel.com> Cc: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: Mauro Carvalho Chehab <m.chehab@samsung.com> Cc: kbuild-all@01.org Cc: linux-edac <linux-edac@vger.kernel.org> Link: http://lkml.kernel.org/r/20150605112426.GA97073@lkp-sb04Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Thor Thayer 提交于
The Arria10 SDRAM and ECC system differs significantly from the Cyclone5 and Arria5 SoCs. This patch adds support for the Arria10 SoC. 1) IRQ handler needs to support SHARED IRQ 2) Support sberr and dberr address reporting. Signed-off-by: NThor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-4-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Thor Thayer 提交于
The Arria10 SoC uses a completely different SDRAM controller from the earlier CycloneV and ArriaV SoCs. This patch abstracts the SDRAM bits for the CycloneV/ArriaV SoCs in preparation for the Arria10 support. Signed-off-by: NThor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-3-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Thor Thayer 提交于
The Arria10 SOC uses a completely different SDRAM controller from the earlier CycloneV and ArriaV SoCs. The memory size is calculated in the bootloader and passed via the device tree. Using this device tree size is more generic than using the register fields to calculate the memory size for different SDRAM controllers. Signed-off-by: NThor Thayer <tthayer@opensource.altera.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: devicetree@vger.kernel.org Cc: dinguyen@opensource.altera.com Cc: galak@codeaurora.org Cc: grant.likely@linaro.org Cc: ijc+devicetree@hellion.org.uk Cc: linux-arm-kernel@lists.infradead.org Cc: linux-edac <linux-edac@vger.kernel.org> Cc: m.chehab@samsung.com Cc: mark.rutland@arm.com Cc: pawel.moll@arm.com Cc: robh+dt@kernel.org Cc: tthayer.linux@gmail.com Link: http://lkml.kernel.org/r/1433428128-7292-2-git-send-email-tthayer@opensource.altera.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Aravind Gopalakrishnan 提交于
Provide information about each injection file and its usage for ease of use and in-band documentation. This is a good idea adapted from ftrace. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Cc: Steven Rostedt <rostedt@goodmis.org> Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1433277362-10911-7-git-send-email-Aravind.Gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 24 6月, 2015 1 次提交
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由 Aravind Gopalakrishnan 提交于
Add per-file permissions to the dfs_fls[] array. In a later patch, we will add a README file that needs different permissions. Hence the move here to add a perm field. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1433277362-10911-6-git-send-email-Aravind.Gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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- 03 6月, 2015 7 次提交
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由 Aravind Gopalakrishnan 提交于
Use strings such as "hw" or "sw" to indicate the type of error injection to be performed. Current flags attribute derives the meanings of values that can be programmed into it from asm/mce.h. Moving to defined strings for the attribute allows this module to be self-sufficient and removes the dependency. Also, we can introduce new flags as and when needed without having to worry about conflicting with the flags already defined in asm/mce.h. Also, modify do_inject() to use the newly defined injection_type enum to figure out the injection mechanism we need to use Suggested-by: NBorislav Petkov <bp@suse.de> Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1433277362-10911-4-git-send-email-Aravind.Gopalakrishnan@amd.com [ Use strstrip() return value. ] Signed-off-by: NBorislav Petkov <bp@suse.de>
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由 Aravind Gopalakrishnan 提交于
The number of banks for a given processor is encoded in MSR_IA32_MCG_CAP[7:0]. So obtain the value from that MSR and use it for sanity checking in inj_bank_set() instead of doing a family/model check. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Link: http://lkml.kernel.org/r/1432753418-2985-3-git-send-email-Aravind.Gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Aravind Gopalakrishnan 提交于
inj_bank_get() is generic enough that we can use the MCE_INJECT_GET macro instead. No functionality change. Signed-off-by: NAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> Cc: linux-edac <linux-edac@vger.kernel.org> Cc: mchehab@osg.samsung.com Cc: x86-ml <x86@kernel.org> Link: http://lkml.kernel.org/r/1433277362-10911-2-git-send-email-Aravind.Gopalakrishnan@amd.comSigned-off-by: NBorislav Petkov <bp@suse.de>
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由 Tony Luck 提交于
Basic support for the single socket Broadwell-DE processor was added back in commit 1f39581a sb_edac: Add support for Broadwell-DE processor This patch extends Broadwell support to cover the two socket "-EP" and four socket "-EX" versions of Broadwell. Only tested on the 2 socket - but this code is largely cloned from the Haswell path. Signed-off-by: NTony Luck <tony.luck@intel.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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由 Tony Luck 提交于
First noticed a problem on a 4 socket machine where EDAC only reported half the DIMMS. Tracked this down to the code that assumes that systems with two home agents only have two memory channels on each agent. This is true on 2 sockect ("-EP") machines. But four socket ("-EX") machines have four memory channels on each home agent. The old code would have had problems on two socket systems as it did a shuffling trick to make the internals of the code think that the channels from the first agent were '0' and '1', with the second agent providing '2' and '3'. But the code didn't uniformly convert from {ha,channel} tuples to this internal representation. New code always considers up to eight channels. On a machine with a single home agent these map easily to edac channels 0, 1, 2, 3. On machines with two home agents we map using: edac_channel = 4*ha# + channel So on a -EP machine where each home agent supports only two channels we'll fill in channels 0, 1, 4, 5, and on a -EX machine we use all of 0, 1, 2, 3, 4, 5, 6, 7. [mchehab@osg.samsung.com: fold a fixup patch as per Tony's request and fixed a few CodingStyle issues] Signed-off-by: NTony Luck <tony.luck@intel.com> Acked-by: NAristeu Rozanski <aris@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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由 Tony Luck 提交于
typo: "a7mode" chooses whether to use bits {8, 7, 9} or {8, 7, 6} in the algorithm to spread access between memory resources. But the non-a7mode path was incorrectly using GET_BITFIELD(addr, 7, 9) and so picking bits {9, 8, 7} thinko: BIT(1) of the dram_rule registers chooses whether to just use the {8, 7, 6} (or {8, 7, 9}) bits mentioned above as they are, or to XOR them with bits {18, 17, 16} but the code inverted the test. We need the additional XOR when dram_rule{1} == 0. Signed-off-by: NTony Luck <tony.luck@intel.com> Acked-by: NAristeu Rozanski <aris@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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由 Tony Luck 提交于
Currently set to "6", but the reset of the code will dynamically allocate as needed. We need to go to "8" today, but drop the check completely to save doing this again when we need even larger numbers. Signed-off-by: NTony Luck <tony.luck@intel.com> Acked-by: NAristeu Rozanski <aris@redhat.com> Signed-off-by: NMauro Carvalho Chehab <mchehab@osg.samsung.com>
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