1. 07 6月, 2017 1 次提交
  2. 06 6月, 2017 1 次提交
    • V
      drm/i915: Workaround VLV/CHV DSI scanline counter hardware fail · ec1b4ee2
      Ville Syrjälä 提交于
      The scanline counter is bonkers on VLV/CHV DSI. The scanline counter
      increment is not lined up with the start of vblank like it is on
      every other platform and output type. This causes problems for
      both the vblank timestamping and atomic update vblank evasion.
      
      On my FFRD8 machine at least, the scanline counter increment
      happens about 1/3 of a scanline ahead of the start of vblank (which
      is where all register latching happens still). That means we can't
      trust the scanline counter to tell us whether we're in vblank or not
      while we're on that particular line. In order to keep vblank
      timestamping in working condition when called from the vblank irq,
      we'll leave scanline_offset at one, which means that the entire
      line containing the start of vblank is considered to be inside
      the vblank.
      
      For the vblank evasion we'll need to consider that entire line
      to be bad, since we can't tell whether the registers already
      got latched or not. And we can't actually use the start of vblank
      interrupt to get us past that line as the interrupt would fire
      too soon, and then we'd up waiting for the next start of vblank
      instead. One way around that would using the frame start
      interrupt instead since that wouldn't fire until the next
      scanline, but that would require some bigger changes in the
      interrupt code. So for simplicity we'll just poll until we get
      past the bad line.
      
      v2: Adjust the comments a bit
      
      Cc: stable@vger.kernel.org
      Cc: Jonas Aaberg <cja@gmx.net>
      Tested-by: NJonas Aaberg <cja@gmx.net>
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99086Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20161215174734.28779-1-ville.syrjala@linux.intel.comTested-by: NMika Kahola <mika.kahola@intel.com>
      Reviewed-by: NMika Kahola <mika.kahola@intel.com>
      ec1b4ee2
  3. 01 6月, 2017 1 次提交
    • M
      drm/i915/skl+: consider max supported plane pixel rate while scaling · 73b0ca8e
      Mahesh Kumar 提交于
      A display resolution is only supported if it meets all the restrictions
      below for Maximum Pipe Pixel Rate.
      
      The display resolution must fit within the maximum pixel rate output
      from the pipe. Make sure that the display pipe is able to feed pixels at
      a rate required to support the desired resolution.
      For each enabled plane on the pipe {
          If plane scaling enabled {
      	Horizontal down scale amount = Maximum[1, plane horizontal size /
      		    scaler horizontal window size]
      	Vertical down scale amount = Maximum[1, plane vertical size /
      		    scaler vertical window size]
      	Plane down scale amount = Horizontal down scale amount *
      		    Vertical down scale amount
      	Plane Ratio = 1 / Plane down scale amount
          }
          Else {
      	Plane Ratio = 1
          }
          If plane source pixel format is 64 bits per pixel {
      	Plane Ratio = Plane Ratio * 8/9
          }
      }
      
      Pipe Ratio = Minimum Plane Ratio of all enabled planes on the pipe
      
      If pipe scaling is enabled {
          Horizontal down scale amount = Maximum[1, pipe horizontal source size /
      		scaler horizontal window size]
          Vertical down scale amount = Maximum[1, pipe vertical source size /
      		scaler vertical window size]
          Note: The progressive fetch - interlace display mode is equivalent to a
      		2.0 vertical down scale
          Pipe down scale amount = Horizontal down scale amount *
      		Vertical down scale amount
          Pipe Ratio = Pipe Ratio / Pipe down scale amount
      }
      
      Pipe maximum pixel rate = CDCLK frequency * Pipe Ratio
      
      In this patch our calculation is based on pipe downscale amount
      (plane max downscale amount * pipe downscale amount) instead of Pipe
      Ratio. So,
      max supported crtc clock with given scaling = CDCLK / pipe downscale.
      Flip will fail if,
      current crtc clock > max supported crct clock with given scaling.
      
      Changes since V1:
       - separate out fixed_16_16 wrapper API definition
      Changes since V2:
       - Fix buggy crtc !active condition (Maarten)
       - use intel_wm_plane_visible wrapper as per Maarten's suggestion
      Changes since V3:
       - Change failure return from ERANGE to EINVAL
      Changes since V4:
       - Rebase based on previous patch changes
      Changes since V5:
       - return EINVAL instead of continue (Maarten)
      Changes since V6:
       - Improve commit message
       - Address review comment
      Changes since V7:
       - use !enable instead of !active
       - rename config variable for consistency (Maarten)
      Signed-off-by: NMahesh Kumar <mahesh1.kumar@intel.com>
      Reviewed-by: NMatt Roper <matthew.d.roper@intel.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170526151546.25025-4-mahesh1.kumar@intel.com
      73b0ca8e
  4. 30 5月, 2017 2 次提交
  5. 22 5月, 2017 1 次提交
  6. 16 5月, 2017 2 次提交
  7. 11 5月, 2017 14 次提交
  8. 10 5月, 2017 6 次提交
  9. 26 4月, 2017 1 次提交
  10. 15 4月, 2017 1 次提交
  11. 12 4月, 2017 1 次提交
  12. 07 4月, 2017 3 次提交
  13. 06 4月, 2017 1 次提交
    • D
      drm/fb-helper: Give up on kgdb for atomic drivers · 9c79e0b1
      Daniel Vetter 提交于
      It just doesn't work. It probably stopped working way, way before that
      (e.g. i915 grabbed random mutexes all over in modeset code at least
      since gen6), but with atomic and all the ww_mutex stuff it's indeed
      hopeless.
      
      Remove ->mode_set_base_atomic from the 2 atomic drivers (i915 and
      nouveau) that still had one (both had dummy implementations already
      anyway), and shunt atomic drivers in the helpers debug_enter/leave
      functions.
      
      I'll leave the code in for radeon and amdgpu, but I think as soon as
      amdgpu is atomic we should think about just ripping it out. Only
      having it around for radeon and pre-nv50 is rather pointless. This
      would also allow us to nuke all that code from fbdev.
      
      Funny part is that _all_ kms drivers set this hook, despite that no
      one else provides the required ->mode_set_base_atomic implementation.
      
      The reason I'm jumping on this is that I want to wire up a full
      acquire ctx for the benefit of atomic drivers, everywhere. And the
      debug_enter/leave implementations call ->gamma_set. And there's just
      no way ever we can create an acquire_ctx in the nmi context of kgdb.
      
      Cc: Ben Skeggs <bskeggs@redhat.com>
      Cc: Alex Deucher <alexander.deucher@amd.com>
      Reviewed-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Acked-by: NAlex Deucher <alexander.deucher@amd.com>
      Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/20170403083304.9083-11-daniel.vetter@ffwll.ch
      9c79e0b1
  14. 05 4月, 2017 3 次提交
  15. 30 3月, 2017 2 次提交