The NAND framework provides several helpers to query timing modes supported
by a NAND chip, but this implies that all NAND controller drivers have
to implement the same timings selection dance. Also currently NAND
devices can be resetted at arbitrary places which also resets the timing
for ONFI chips to timing mode 0.

Provide a common logic to select the best timings based on ONFI or
->onfi_timing_mode_default information. Hook this into nand_reset()
to make sure the new timing is applied each time during a reset.

NAND controller willing to support timings adjustment should just
implement the ->setup_data_interface() method.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

The nand layer will need ONFI mode 0 to use it as timing mode
before and right after reset.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

onfi_init_data_interface() initializes a data interface with
values from a given ONFI mode.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

struct nand_data_interface is the designated type to pass to
the NAND drivers to configure the timing. To simplify further
patches convert the onfi_sdr_timings array from type struct
nand_sdr_timings nand_data_interface.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

When NAND devices are resetted some initialization may have to be done,
like for example they have to be configured for the timing mode that
shall be used. To get a common place where this initialization can be
implemented create a nand_reset() function. This currently only issues
a NAND_CMD_RESET to the NAND device. The places issuing this command
manually are replaced with a call to nand_reset().
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Some Keystone devices (e.g. K2G) include a OMAP NAND IP.
Allow the NAND driver to be usable for both
Keystone and OMAP devices.
Signed-off-by: NRoger Quadros <rogerq@ti.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This patch adds big endian and ONFI support for various iProc based
SoCs that use the core brcmstb NAND controller

This patch was originally implemented by Prafulla Kota
<prafulla.kota@broadcom.com> and fully tested on iProc based NS2 SVK
Signed-off-by: NPrafulla Kota <prafulla.kota@broadcom.com>
Signed-off-by: NRay Jui <ray.jui@broadcom.com>
Reviewed-by: NKamal Dasu <kdasu.kdev@gmail.com>
Acked-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

If erasing or writing the BBT fails, we should mark the current BBT
block as bad and use the BBT descriptor to scan for the next available
unused block in the BBT. We should only return a failure if there isn't
any space left.
Signed-off-by: NKyle Roeschley <kyle.roeschley@ni.com>
Suggested-by: NJeff Westfahl <jeff.westfahl@ni.com>
Tested-by: NKyle Roeschley <kyle.roeschley@ni.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This clarifies the write_bbt() function by removing the write label
and simplifying the error/exit path.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: NKyle Roeschley <kyle.roeschley@ni.com>

In the ONFI spec, the tRR_min entry is defined before the tRST_max one.
Reoder the definition to make it easier to review.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

ONFI 4.0 spec defines different values for the tADL_min timing.
Since we don't want to have different timings depending on the ONFI
version, we just set tADL_min to the maximum value (the one specified
in the ONFI 4.0 spec).
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

change the way to calculate pagesize to get correct free oob space for
legacy_set_geometry function.
Signed-off-by: NHan Xu <han.xu@nxp.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Some build tools noticed that 'cookie' is being set but not used. Might
as well catch the errors here and handle them the same way we handle
other DMA prep steps.
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The driver registered for CPU frequency transitions to recalculate its
clock when ARM clock frequency changes (ratio between frequencies of
ARM's parent clock (fclk) and clock for peripherals remains fixed).

This is needed only on S3C24xx platform when cpufreq driver is enabled
so limit the ifdef to respective cpufreq Kconfig.
Suggested-by: NMarek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Using "goto" and "switch" statement only makes it harder to follow
control flow and doesn't bring any advantages. Rewrite the code to avoid
using "goto".
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

If no user specified chip->select_chip() function is provided, code in
nand_base.c will automatically set this hook to nand_select_chip(),
which in turn depends on chip->cmd_ctrl() hook being valid. Not
providing both of those functions in NAND controller driver (for example
by mistake) will result in a bit cryptic segfault. Same is true for
chip->cmdfunc().

To avoid the above scenario add a check in nand_scan_dent and error out
if cmd_ctrl() is not provided.
Suggested-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Suggested-by: NBrian Norris <computersforpeace@gmail.com>
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Config MTD_NAND_FSL_IFC is already located inside 'if MTD_NAND'
statment, so there's no need to explicitly specify it as a dependency.
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

MTD_NAND_FSL_ELBC selects FSL_LBC that in turn depends on FSL_SOC, so
depending on PPC instead of FSL_SOC leads to this message:

	  warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC &&
	  MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct
	  dependencies (FSL_SOC)

when doing

	  make ARCH=powerpc \
	       CROSS_COMPILE=powerpc-e500v2-linux-gnuspe- \
	       allmodconfig"

Changing dependency to FSL_SOC fixes that.
Signed-off-by: NAndrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The code to initialize a struct nand_hw_control is duplicated across
several drivers. Factorize it using an inline function.
Signed-off-by: NMarc Gonzalez <marc_gonzalez@sigmadesigns.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

nand_do_write_ops() determines if it is writing a partial page with the
formula:
	part_pagewr = (column || writelen < (mtd->writesize - 1))

When 'writelen' is exactly 1 byte less than the NAND page size the formula
equates to zero, so the code doesn't process it as a partial write,
although it should.
As a consequence the function remains in the while(1) loop with 'writelen'
becoming 0xffffffff and iterating endlessly.

The bug may not be easy to reproduce in Linux since user space tools
usually force the padding or round-up the write size to a page-size
multiple.
This was discovered in U-Boot where the issue can be reproduced by
writing any size that is 1 byte less than a page-size multiple.
For example, on a NAND with 2K page (0x800):
	=> nand erase.part <partition>
	=> nand write $loadaddr <partition> 7ff

[Editor's note: the bug was added in commit 29072b96, but moved
around in commit 66507c7b ("mtd: nand: Add support to use nand_base
poi databuf as bounce buffer")]

Fixes: 29072b96 ("[MTD] NAND: add subpage write support")
Signed-off-by: NHector Palacios <hector.palacios@digi.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Change the BUG_ON() condition in brcmnand_send_cmd() which checks for
the interrupt status "controller ready" bit to a WARN_ON.

There is no good reason to kill the system when this condition occur
because we could have systems which listed the NAND controller as
available (e.g: from Device Tree), but the NAND chip could be
malfunctioning and not responding.
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: NBrian Norris <computersforpeace@gmail.com>
Reviewed-by: NKamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

In case of error, the function dma_request_chan() returns ERR_PTR() and
never returns NULL. The NULL test in the return value check should be
replaced with IS_ERR().

Fixes: aa7abd31 ('mtd: nand: omap2: Support parsing dma channel
information from DT')
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

commit c9711ec5 ("mtd: nand: omap: Clean up device tree support")
removes the check for the old elm phandle binding.
Add it again to keep backward compatibility.

Fixes: commit c9711ec5 ("mtd: nand: omap: Clean up device tree support")
Signed-off-by: NTeresa Remmet <t.remmet@phytec.de>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

This patch enables IFC NAND support on ARM layerscape platform.
It fixes the dependency to enable NAND. The include files are being modified
to ensure complilation for both PowerPC and ARM architectures.
Signed-off-by: NRaghav Dogra <raghav.dogra@nxp.com>
Acked-by: NScott Wood <oss@buserror.net>
Signed-off-by: NBrian Norris <computersforpeace@gmail.com>

Emails will bounce from my imgtec address, so update it to a new one.
Signed-off-by: NHarvey Hunt <harvey.hunt@imgtec.com>
Cc: Harvey Hunt <harveyhuntnexus@gmail.com>
Cc: linux-mtd@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

I moved the sanity check on ecc->size before the allocation so that we
don't leak memory on error.

Fixes: 05af074a4b73 ('mtd: nand: sunxi: check ecc->size values')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The NAND controller on some sun8i chips needs its reset line to be
deasserted before they can enter working state.
Signed-off-by: NIcenowy Zheng <icenowy@aosc.xyz>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Instead of using IO_ADDR_W and IO_ADDR_R use an own pointer to the NAND
controller memory area.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This driver needs a special write_buf and read_buf function, because we
have to read from a specific address to tell the controller this is a
read from the nand controller.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Extract the functions to read and write to the register of the NAND
flash controller.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The external Bus Unit (EBU) can control different flash devices, but
these NAND flash commands have to be atomic and should not be
interrupted in between. Lock the EBU from the beginning of the command
till the end by moving the lock to the chip select.
Signed-off-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

nand_scan() already resets the NAND flash chip, this driver does not
have to call it manually. The xway_reset_chip() functions does the same
as the normal NAND reset function. The waiting for the NAND_WAIT_WR_C
is done in xway_cmd_ctrl().
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The ->cmd_ctrl() function is adjusting the ->IO_ADDR_W value depending
on the command type each time NAND_CTRL_CHANGE is passed. This is not
only useless but can lead to an ->IO_ADDR_W corruption.

Get rid of this logic and rely on the NAND_CLE and NAND_ALE flags to
deduce the iomem address to write the cmd argument to.
Signed-off-by: NJohn Crispin <john@phrozen.org>
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Instead of hacking this into the plat_nand driver just make this a
normal nand driver.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

This adds some register documentation which should make it easier to
understand how this controller works. In addition it makes now use of
BIT() macro and adds some more defines.
Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Implement ecc->write_subpage() to prevent core code from assigning this
hook to nand_write_subpage_hwecc(). This default implementation tries
to call ecc->hwctl() which in our case is NULL, thus leading to a NULL
pointer dereference.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Verify that the ecc->size value is either 512 or 1024 bytes.
This should always be the case if this field was assigned to the
nand->ecc_step_size_ds value, but can be wrong when the user overloaded
this value with the nand-ecc-step-size DT property.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

Switching to 1k ECC blocks when possible provides better resistance against
concentrated bitflips. Say you have those two configurations:

1/ 16bits/512bytes
2/ 32bits/1024bytes

Both of them require the same amount of ECC bytes (only true for this
specific engine), but the second config allows you to correct the case
where most of your bitflips are concentrated in a single 512bytes portion.

This fact makes the 1k ECC block size more advantageous than the 512bytes
one.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>

The column address passed to the RNDOUT operation was missing the page
size offset.
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Fixes: 614049a8 ("mtd: nand: sunxi: add support for DMA assisted operations")

Add support for mediatek's SDG1 NFC nand controller embedded in SoC
2701
Signed-off-by: NJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Tested-by: NXiaolei Li <xiaolei.li@mediatek.com>