Instead of reading current vsel value from the VP's voltage register,
just use current nominal voltage translated into vsel via the PMIC.

Doing this allows VC bypass scaling to work even without a VP configured.
Signed-off-by: NKevin Hilman <khilman@ti.com>

On OMAP3+, all VC channels have the the same bitfield ordering for all
VC channels, except the OMAP4 MPU channel.  This appears to be a freak
accident as all other VC channel (including OMAP5) have the standard
configuration.  Handle the mutant case by adding a per-channel flag
to signal the deformity and handle it during VC init.

Special thanks to Nishanth Menon <nm@ti.com> for finding this problem
and for proposing the initial solution.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

Remove hard-coded I2C configuration in favor of settings that can be
configured from PMIC-specific values.  Currently only high-speed mode
and the master-code value are supported, since they were the only
fields currently used, but extending this is now trivial.

Thanks to Nishanth Menon <nm@ti.com> for reporting/fixing a sparse
problem and making omap_vc_i2c_init() static, as well as finding and
fixing a problem with the shift/mask of mcode.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Move structure containing PMIC configurable settings into struct
voltagedomain.  In the process, rename from omap_volt_pmic_info to
omap_voltdm_pmic (_info suffix is not helpful.)

No functional changes.
Signed-off-by: NKevin Hilman <khilman@ti.com>

VC channel configuration is programmed based on settings coming from
the PMIC configuration.

Currently, the VC channel to PMIC mapping is a simple one-to-one
mapping.  Whenever a VC channel parameter is configured (i2c slave
addres, PMIC register address, on/ret/off command), the corresponding
bits are enabled in the VC channel configuration register.

If necessary, the programmability of channel configuration settings
could be extended to board/PMIC files, however, because this patch
changes the channel configuration to be programmed based on existing
values from the PMIC settings, it may not be required.

Also note that starting with OMAP4, where there are more than 2
channels, one channel is identified as the "default" channel.  When
any of the bits in the channel config for the other channels are zero,
it means to use the default channel.  The OMAP4 TRM (at least through
NDA version Q) is wrong in describing which is the default channel.
The default channel on OMAP4 is MPU, not CORE as decribed in the TRM.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Configuring the on/onlp/ret/off command values is common to OMAP3 & 4.
Move from OMAP3-only init into common VC init.
Signed-off-by: NKevin Hilman <khilman@ti.com>

- add setup_time field to struct omap_vc_channel (init'd from PMIC data)
- use VC/VP register access helper for read/modify/write
- move VFSM structure from omap_vdd_info into struct voltagedomain
- remove redunant _data suffix from VFSM structures and variables
- remove voltsetup_shift, use ffs() on the mask value to find the shift
Signed-off-by: NKevin Hilman <khilman@ti.com>

The PMIC configurable variables should be isolated to VC initialization.
The rest of the VC functions (like VC bypass) should use the i2c slave address
and voltage register address fields from struct omap_vc_channel.
Signed-off-by: NKevin Hilman <khilman@ti.com>

- support both voltage register address and command register address
  for each VC channel
- add fields for voltage register address (volra) and command register
  address (cmdra) to struct omap_vc_channel
- use VC/VP register access read/modify/write helper
- remove volra_shift field (use __ffs(mask) for shift value)
- I2C addresses 10-bit, change size to u16
Signed-off-by: NKevin Hilman <khilman@ti.com>

- Add an i2c_slave_address field to the omap_vc_channel
- use VC/VP read/modify/write helper instead of open-coding
- remove smps_sa_shift, use __ffs(mask) for shift value
- I2C addresses 10-bit, change size to u16

Special thanks to Shweta Gulati <shweta.gulati@ti.com> for suggesting
the use of __ffs(x) instead of ffs(x) - 1.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Convert VC/VP register access to use PRM VC/VP accessor functions.  In
the process, move the read/write function pointers from vdd_info into
struct voltagedomain.

No functional changes.

Additional cleanup:
- remove prm_mod field from  VC/VP data structures, the PRM register
  access functions know which PRM module to use.
Signed-off-by: NKevin Hilman <khilman@ti.com>

On OMAP3+, the voltage controller (VC) and voltage processor (VP) are
inside the PRM.  Add some PRM helper functions for register access to
these module registers.

Thanks to Nishanth Menon for finding/fixing a sparse problem.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

Replace the VP tranxdone check/clear with helper functions from the
PRM layer.

In the process, remove prm_irqst_* voltage structure fields for IRQ
status checking which are no longer needed.

Since these reads/writes of the IRQ status bits were the only PRM
accesses that were not to VC/VP registers, this allows the rest of the
register accesses in the VC/VP code to use VC/VP specific register
access functions (done in the following patch.)
Signed-off-by: NKevin Hilman <khilman@ti.com>

Add SoC specific PRM VP helper functions for checking and clearing
the VP transaction done status.

Longer term, these events should be handled by the forthcoming PRCM
interrupt handler.
Signed-off-by: NKevin Hilman <khilman@ti.com>

The VC layer can support PMICs with separate voltage and command
registers by putting the different registers in the PRM_VC_SMPS_VOL_RA
and PRCM_VC_SMPS_CMD_RA registers respectively.

The PMIC data must supply at least a voltage register address
(volt_reg_addr).  The command register address (cmd_reg_addr) is
optional.  If the PMIC data does not supply a separate command
register address, the VC will use the voltage register address for both.
Signed-off-by: NKevin Hilman <khilman@ti.com>

This patch is primarily a move of VP specific code from voltage.c into
its own code in vp.c and adds prototypes to vp.h

No functional changes, except debugfs...

VP debugfs moved to 'vp' subdir of <debugfs>/voltage/ and 'vp_'
prefixes removed from all debugfs filenames.
Signed-off-by: NKevin Hilman <khilman@ti.com>

VC is initialized first, set default scaling method to VC bypass.
If/when VP is initialized, default scaling method will be changed to
VP force-update.

Enabling VC bypass as default as soon as VC is initialized allows for
VC bypass scaling to work when no VP is configured/initialized for a
given voltage domain.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Move the VC instance struct from omap_vdd_info into struct voltagedomain.
While moving, perform some misc. renames for readability.

No functional changes.

Summary of renames:
- rename omap_vc_instance to omap_vc_channel, since there is only
  one instance of the VC IP and this actually represents channels
  using TRM terminology.
- rename 'vc_common' field of VC channel which led to:
  s/vc->vc_common/vc->common/
- remove redundant '_data' suffix
- OMAP3: vc1 --> vc_mpu, vc2 --> vc_core
- omap_vc_bypass_scale_voltage() -> omap_vc_bypass_scale()
Signed-off-by: NKevin Hilman <khilman@ti.com>

merge

As part of the voltage layer cleanup, split out VC specific code into
a dedicated VC layer.  This patch primarily just moves VC code from
voltage.c into vc.c, and adds prototypes to vc.h.

No functional changes.

For readability, each function was given a local 'vc' pointer:

    struct omap_vc_instance_data *vc = voltdm->vdd->vc_data;

and a global replace of s/vdd->vc_data/vc/ was done.

Also vc_init was renamed to vc_init_channel to reflect that this is
per-VC channel initializtion.
Signed-off-by: NKevin Hilman <khilman@ti.com>

When a powerdomain is registered and it has an associated voltage domain,
add the powerdomain to the voltagedomain using voltdm_add_pwrdm().

Also add voltagedomain iterator helper functions to iterate over all
registered voltagedomains and all powerdomains associated with a
voltagedomain.

Modeled after a similar relationship between clockdomains and powerdomains.
Signed-off-by: NKevin Hilman <khilman@ti.com>

When a powerdomain is registered, lookup the voltage domain by name
and keep a pointer to the containing voltagedomain in the powerdomain
structure.

Modeled after similar method between powerdomain and clockdomain layers.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Add voltage domain name to indicate which voltagedomain each
powerdomain is in.

The fixed voltage domain like ldo_wakeup for emu and wkup power
domain is added too.
Signed-off-by: NBenoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[khilman@ti.com]: renamed wakeup domain: s/ldo_wakeup/wakeup/
Signed-off-by: NKevin Hilman <khilman@ti.com>

Add voltage domain name to indicate which voltagedomain each
powerdomain is in.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Create basic voltagedomains for OMAP2 and associate OMAP2 powerdomains
with the newly created voltage domains.

While here, update copyright on powerdomain data to 2011.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Each powerdomain is associated with a voltage domain.  Add an entry to
struct powerdomain where the enclosing voltagedomain can be
referenced.

Modeled after similar relationship between clockdomains and powerdomains.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Add a 'bool scalable' flag to the struct powerdomain and set it for
the scalable domains on OMAP3 and OMAP4.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Add wakeup voltage domain so that the wakeup powerdomain can have an
associated powerdomain.  Note that the scalable flat is not set for
the this voltagedomain, so it will not be fully initialized like
scalable voltage domains.
Signed-off-by: NKevin Hilman <khilman@ti.com>

This voltage domain (a.k.a. VDD1) contains both the MPU and the IVA, so
rename appropriately.

Also fixup any users of the "mpu" name to use "mpu_iva"
Signed-off-by: NKevin Hilman <khilman@ti.com>

Start cleaning up the voltage layer to have a voltage domain layer
that resembles the structure of the existing clock and power domain
layers.  To that end:

- move the 'struct voltagedomain' out of 'struct omap_vdd_info' to
  become the primary data structure.

- convert any functions taking a pointer to struct omap_vdd_info into
  functions taking a struct voltagedomain pointer.

- convert the register & initialize of voltage domains to look like
  that of powerdomains

- convert omap_voltage_domain_lookup() to voltdm_lookup(), modeled
  after the current powerdomain and clockdomain lookup functions.

- omap_voltage_late_init(): only configure VDD info when
  the vdd_info struct is non-NULL
Signed-off-by: NKevin Hilman <khilman@ti.com>

The prm_irqst_reg is not part of the VP.  Move it up into the common
voltage domain struct.
Signed-off-by: NKevin Hilman <khilman@ti.com>

Eliminate need for global variables for the various PRM module offsets by
making them part of the VP/VC common structures

Eventually, these will likely be moved again, or more likely removed
when VP/VC code is isolated, but for now just getting rid of them as
global variabes so that the voltage domain initialization can be
cleaned up.
Signed-off-by: NKevin Hilman <khilman@ti.com>

The voltage domain pointer currently in struct omap_hwmod is not used
and does not belong here.  Instead, voltage domains will be associated
with powerdomains in forthcoming patches.
Acked-by: NPaul Walmsley <paul@pwsan.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

At Tony's request, remove the omap_chip bitmasks from the powerdomain
definitions.  Instead, initialize powerdomains based on one or more
lists that are applicable to a particular SoC family, variant, and
silicon revision.

Gražvydas Ignotas <notasas@gmail.com> found and reported a bug in a
related patch that also applied to this patch - thanks Gražvydas.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Gražvydas Ignotas <notasas@gmail.com>

In preparation for OMAP_CHIP() removal, split pwrdm_init() into three
functions.  This allows some of them to be called multiple times: for
example, pwrdm_register_pwrdms() can be called once to register
powerdomains that are common to a group of SoCs, and once to register
powerdomains that are specific to a single SoC.

The appropriate order to call these functions - which is enforced
by the code - is:

1. pwrdm_register_platform_funcs()
2. pwrdm_register_pwrdms() (can be called multiple times)
3. pwrdm_complete_init()

Convert the OMAP2, 3, and 4 powerdomain init code to use these new
functions.

While here, improve documentation, and increase CodingStyle
conformance by shortening some local variable names.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

At Tony's request, remove the omap_chip bitmasks from the clockdomain
and clockdomain dependency definitions.  Instead, initialize
clockdomains based on one or more lists that are applicable to a
particular SoC family, variant, and silicon revision.

Tony Lindgren <tony@atomide.com> found a bug in a previous version of this
patch - thanks Tony.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>

In preparation for OMAP_CHIP() removal, split clkdm_init() into four
functions.  This allows some of them to be called multiple times: for
example, clkdm_register_clkdms() can be called once to register
clockdomains that are common to a group of SoCs, and once to register
clockdomains that are specific to a single SoC.

The appropriate order to call these functions - which is enforced
by the code - is:

1. clkdm_register_platform_funcs()
2. clkdm_register_clkdms() (can be called multiple times)
3. clkdm_register_autodeps() (optional; deprecated)
4. clkdm_complete_init()

Convert the OMAP2, 3, and 4 clockdomain init code to use these new
functions.

While here, improve documentation, and increase CodingStyle
conformance by shortening some local variable names.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>

The OMAP_REVBITS_* macros are just used as otherwise meaningless
aliases for the numbers zero through five, so remove these macros.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
Tested-by: NAbhilash Koyamangalath <abhilash.kv@ti.com>

omap3_cpuinfo() contains essentially duplicated code from
omap3_check_revision(), just for the purpose of determining the chip ES level.
Set the cpu_rev char array pointer in omap3_check_revision() instead,
and drop the now-useless code from omap3_cpuinfo().
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
Tested-by: NAbhilash Koyamangalath <abhilash.kv@ti.com>

Emit a warning to the console in omap3_check_revision() if that code
cannot determine what type of SoC the system is currently running on.

Remove some extra whitespace, remove some duplicate code, and
add an appropriate comment to a fallthrough case.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Hemant Pedanekar <hemantp@ti.com>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
Tested-by: NAbhilash Koyamangalath <abhilash.kv@ti.com>

Use explicit revision codes for OMAP/AM 3505/3517 ES levels, as the rest
of the OMAP2+ SoCs do in mach-omap2/cpu.c.
Signed-off-by: NPaul Walmsley <paul@pwsan.com>
Cc: Sanjeev Premi <premi@ti.com>
Tested-by: NIgor Grinberg <grinberg@compulab.co.il>
Tested-by: NAbhilash Koyamangalath <abhilash.kv@ti.com>