Correct SPI clock frequency division factor rounding, preventing clock rates
higher than the maximum specified clock frequency being used.

When specifying spi-max-frequency = <10000000> in the device tree,
the resulting frequency was 11.1 MHz, with spibrg being 133333332.

According to the freescale data sheet [1], the spi clock rate is
spiclk = spibrg / (4 * (pm+1))

The existing code calculated
  pm = mpc8xxx_spi->spibrg / (hz * 4); pm--;
  resulting in pm = (int) (3.3333) - 1 = 2,
  resulting in spiclk = 133333332/(4*(2+1)) = 11111111

  With the fix,
   pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; pm--;
   resulting in pm = (int) (4.3333) - 1 = 3,
   resulting in spiclk = 133333332/(4*(3+1)) = 8333333

   Without the fix, for every desired SPI frequency that
   is not exactly derivable from spibrg, pm will be too
   small due to rounding down, resulting in a too high SPI clock,
   so we need a pm which is one higher.

   For values that are exactly derivable, spibrg will
   be dividable by (hz*4) without remainder, and
   (int) ((spibrg-1)/(hz*4)) will be one lower than
   (int) (spibrg)/(hz*4), which is compensated by adding 1.
   For these values, the fixed version calculates the same pm
   as the unfixed version.

   For all values that are not exactly derivable,
   spibrg will be not dividable by (hz*4) without
   remainder, and (int) ((spibrg-1)/(hz*4)) will be
   the same as (int) (spibrg)/(hz*4), and the calculated pm will
   be one higher than calculated by the unfixed version.

References:
[1] http://www.freescale.com/files/32bit/doc/ref_manual/MPC8315ERM.pdf,
   page 22-10 -> 1398
Signed-off-by: NErnst Schwab <eschwab@online.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

String constants that are continued on subsequent lines with \
are not good.
Signed-off-by: NJoe Perches <joe@perches.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The spi_sh_msiof.c driver presently misconfigures REDG and TEDG. TEDG==0
outputs data at the **rising edge** of the clock and REDG==0 samples data
at the **falling edge** of the clock. Therefore for SPI, TEDG must be
equal to REDG, otherwise the last byte received is not sampled in SPI
mode 3.

This brings the driver in line with the SH7723 HW Reference Manual
settings documented in Figures 20.20 and 20.21 ("SPI Clock and data
timing").
Signed-off-by: NMarkus Pietrek <Markus.Pietrek@emtrion.de>
Acked-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

dw_spi_mmio is dependent on the clock framework. This marks it as such
in Kconfig.
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Minor code style cleanups following comments by Wolfram Sang
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Adds a memory-mapped I/O dw_spi platform device.
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

So that interface drivers could be built as modules
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This allows the switching between transfer modes between 'transmit only',
'receive only' and 'transmit and receive' modes. Due to the design of the SPI
block, changing transfer modes requires that the block be disabled; in doing
so the chipselect line is inherently deasserted and (usually) the attached
device discards its state. Consequentially, switching modes requires that a
platform-specific chipselect function has been defined so that the chipselect
is not dropped during the change.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The 'poll_transfer' function employs a conditional to test whether the
transmit buffer is valid; in doing so, on a receive operation no data is
clocked out, thus no data is clocked in and ultimately errors appear.

This removes the conditional as the transmit function will be set to a null
writer when the transmit buffer is invalid, allowing the driver to clock
0x00 out to the device to receive data from the device.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

As per the function signature.
Signed-off-by: NGeorge Shore <george@georgeshore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

FIFO depth is configurable for each implementation of DW core,
so add a depth detection for those interface drivers who don't set
the fifo_len explicitly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Acked-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Section mismatch in reference from the function dw_spi_add_host()
to the function init_queue()
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

xilinx_spi presently makes some fairly questionable assumptions about I/O
routines, and attempts to assign ioread32/iowrite32 and friends directly
to its own internal function pointers. On many platforms these I/O
routines are macros or wrappers and not actual functions on their own,
resulting in things like:

ERROR: "ioread32be" [drivers/spi/xilinx_spi.ko] undefined!
ERROR: "iowrite32be" [drivers/spi/xilinx_spi.ko] undefined!
ERROR: "iowrite32" [drivers/spi/xilinx_spi.ko] undefined!
ERROR: "ioread32" [drivers/spi/xilinx_spi.ko] undefined!

If xilinx_spi wants to do this sort of casting, it needs to provide its
own wrappers for these, or change how it does accesses completely.

I've opted for the first approach, and the attached silly patch does
that. If someone with the hardware available wants to give the second
option a try that's ok too. In any event, the current code is broken for
at least: arm, avr32, blackfin, microblaze, mn10300, and sh.
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>
Acked-by: NRichard Röjfors <richard.rojfors@pelagicore.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Useful when debugging multiple spi channels.
Signed-off-by: NAlberto Panizzo <maramaopercheseimorto@gmail.com>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Update the MSIOF driver to remove the architecture
speficic spi header file and add err.h. This makes
the driver compile on non-SH architectures.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Now dw_spi core fully supports 3 transfer modes: pure polling,
DMA and IRQ mode. IRQ mode will use the FIFO half empty as
the IRQ trigger, so each interface driver need set the fifo_len,
so that core driver can handle it properly
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Make the driver wait at least  for 1 jiffie before issuing the
warning, no matter what HZ is set to
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Since most of the chip-selects are simply going to be like
gpio_set_value, it would do good to have the same callback type
so that it could simply be made to point at gpio_set_value.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Header for platform specific stuff has been rename to include the SoC
type. Include the new header instead.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add precautionary check before releasing memory region.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The pointer to SPI rate source clock had better be the member of
driver local data structure rather than platform specific.
Also, remove definitions of variable 'sci' that are rendered
useless as a consequence.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The instance of SPI clock for controller and that used for generating
signals ought to be independently handled.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Rename 'struct s3c64xx_spi_cntrlr_info' to lesser wordy
'struct s3c64xx_spi_info'
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

platform_get_irq returns -ENXIO on failure, so !irq was probably
always true.  Make irq a signed variable and compare irq <= 0.  Note
that a return value of zero is still handled as error even though this
could mean irq0.

This is a followup to 305b3228 that
changed the return value of platform_get_irq from 0 to -ENXIO on error.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add support for the QSPI controller found some on Freescale/Motorola
Coldfire MCUs.

Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are
supported.  The hardware drives the MISO, MOSI and SCLK lines, but the chip
selects are managed via GPIO and must be configured by the board code.

The QSPI controller has an 80 byte buffer which allows us to transfer up to 16
words at a time.  For transfers longer than 16 words, we split the buffer in
half so we can update in one half while the controller is operating on the
other half.  Interrupt latencies then ultimately limits our sustained thru-put
to something less than half the maximum speed supported by the part.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The match_table field of the struct of_device_id is constant
in <linux/of_platform.h> so it is worth to make the initialization
data constant.

The semantic match that finds this kind of pattern is as follows:
(http://coccinelle.lip6.fr/)

// <smpl>
@r@
disable decl_init,const_decl_init;
identifier I1, I2, x;
@@
	struct I1 {
	  ...
	  const struct I2 *x;
	  ...
	};
@s@
identifier r.I1, y;
identifier r.x, E;
@@
	struct I1 y = {
	  .x = E,
	};
@c@
identifier r.I2;
identifier s.E;
@@
	const struct I2 E[] = ... ;
@depends on !c@
identifier r.I2;
identifier s.E;
@@
+	const
	struct I2 E[] = ...;
// </smpl>
Signed-off-by: NMárton Németh <nm127@freemail.hu>
Cc: Julia Lawall <julia@diku.dk>
Cc: cocci@diku.dk
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NRobert P. J. Day <rpjday@crashcourse.ca>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds support for a SPI master driver for the
DaVinci series of SOCs
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NMark A. Greer <mgreer@mvista.com>
Signed-off-by: NPhilby John <pjohn@in.mvista.com>
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: Bryan Wu <cooloney@kernel.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Each SPI controller has exactly one CS line and as such doesn't
provide for multi-cs. We implement a workaround to support
multi-cs by _not_ configuring the mux'ed CS pin for each SPI
controller. The CS mechanism is assumed to be fully machine
specific - the driver doesn't even assume some GPIO pin is used
to control the CS.

The driver selects between DMA and POLLING mode depending upon
the xfer size - DMA mode for xfers bigger than FIFO size, POLLING
mode otherwise.

The driver has been designed to be capable of running SoCs since
s3c64xx and till date, for that reason some of the register fields
have been passed via, SoC specific, platform data.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

If len > BUFFER_LEN and !xfer->rx_buf we end up calculating the tx buffer
address as

*tx_dma = xfer->tx_dma + xfer->len - BUFFER_SIZE;

which is constant; i.e.  we just send the last BUFFER_SIZE data over again
until we've reached the right number of bytes.

This patch gets around this by using the /requested/ length when
calculating addresses.

Note there's no way len != *plen when we calculate the rx buffer address
but conceptually we should be using *plen and I don't want someone to come
through later, see the calculations for rx and tx are different and "clean
up" back to what we had.
Signed-off-by: NBen Nizette <bn@niasdigital.com>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add pseudo-DMA by FIQ to the S3C24XX SPI driver.  This allows the driver
to get DMA-like performance where there are either no free DMA channels or
when doing transfers that required both TX and RX data paths.

Since this patch requires the addition of an assembly file to hold the FIQ
code, we rename the module (instead of adding a rename of the .c file to
this patch).  We expect most users are loading this via udev and thus
there should be no change to the userland configuration.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NSimtec Linux Team <linux@simtec.co.uk>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Driver for the Designware SPI core, it supports multipul interfaces like
PCI/APB etc.  User can use "dw_apb_ssi_db.pdf" from Synopsys as HW
datasheet.

[randy.dunlap@oracle.com: fix build]
[akpm@linux-foundation.org: build fix]
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>