This patch removes the ARM architecture mach-pnx4008. No direct support or user
feedback since 2006. Acknowledgements from NXP/Philips and Linux arm-soc
maintainers.
Signed-off-by: NRoland Stigge <stigge@antcom.de>

The CONFIG_PM doesn't actually enable any of the PM callbacks, it
only allows to enable CONFIG_PM_SLEEP and CONFIG_PM_RUNTIME.
This means if CONFIG_PM is used to protect system sleep callbacks
then it may end up unreferenced if only runtime PM is enabled.
Hence protecting sleep callbacks with CONFIG_PM_SLEEP.
Signed-off-by: NLaxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

The master_xfer function returns 0 on success. It should return the number of
successful transactions.
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

In omap_i2c_xfer(), ensure pm_runtime_put() is called, even on
failure.

Without this, after a failed xfer, the runtime PM usecount will have
been incremented, but not decremented causing the usecount to never
reach zero after a failure.  This keeps the device always runtime PM
enabled which keeps the enclosing power domain active, and prevents
full-chip retention/off from happening during idle.
Signed-off-by: NKevin Hilman <khilman@ti.com>
Reviewed-by: NShubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

At this moment in time there is only one known configuration for the
Nomadik I2C driver. By not holding that configuration in the driver
adds some unnecessary overhead in platform code. The configuration
has already been removed from platform code, this patch checks for any
over-riding configurations. If there aren't any, the default is used.

[LinusW says: "Right now this is causing boot regressions so we need it
badly..."]
Acked-by: Nsrinidhi kasagar <srinidhi.kasagar@stericsson.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

With addition of dummy clk_*() calls for non CONFIG_HAVE_CLK cases in
clk.h, there is no need to have clk code enclosed in #ifdef
CONFIG_HAVE_CLK, #endif macros.

pxa i2c also has these dummy macros defined locally.  Remove them as they
aren't required anymore.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: viresh kumar <viresh.linux@gmail.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>

This reverts commit 7c86d44c.
Stephen says:

IIRC, I proposed it before solely to solve some suspend/resume ordering
issues, and Colin Cross NAKd it. These days, deferred probe should make
this change unnecessary.
Reported-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Generate a stop condition after each message marked with I2C_M_STOP.

[JD: Add I2C_FUNC_PROTOCOL_MANGLING.]
Signed-off-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Robofuzz OSIF is a generic USB/iIC interface that embeds an ATMega8A
AVR-RISC microcontroler.

The device is based upon Till Harbaum's i2c-tiny-usb and although it
enhances the original design with further functionnalities it still
maintain compatibility with it with respect to the USB/I2C interface.
Signed-off-by: NEmmanuel Deloget <logout@free.fr>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Byte-by-byte transactions are used primarily for accessing I2C devices
with an SMBus controller.  For these transactions, for each byte that is
read or written, the SMBus controller generates a BYTE_DONE IRQ.  The isr
reads/writes the next byte, and clears the IRQ flag to start the next byte.
On the penultimate IRQ, the isr also sets the LAST_BYTE flag.

There is no locking around the cmd/len/count/data variables, since the
I2C adapter lock ensures there is never multiple simultaneous transactions
for the same device, and the driver thread never accesses these variables
while interrupts might be occurring.

The end result is faster I2C block read and write transactions.

Note: This patch has only been tested and verified by doing I2C read and
write block transfers on Cougar Point 6 Series PCH, as well as I2C read
block transfers on ICH5.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Enable interrupts on more devices. ICH5, ICH7(-M) and ICH10 have been
tested to work OK. ICH8 and ICH9 are expected to work just fine as
they are very close to ICH7 and ICH10.

Ultimately we want to enable this feature on at least every device
since the ICH5, but for now we limit the exposure. We'll enable it for
other devices if we don't get negative feedback.

As a bonus, let the user know when interrupts are used.
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Cc: Daniel Kurtz <djkurtz@chromium.org>

Add a new 'feature' to i2c-i801 to enable using PCI interrupts.
When the feature is enabled, then an isr is installed for the device's
PCI IRQ.

An I2C/SMBus transaction is always terminated by one of the following
interrupt sources: FAILED, BUS_ERR, DEV_ERR, or on success: INTR.

When the isr fires for one of these cases, it sets the ->status variable
and wakes up the waitq.  The waitq then saves off the status code, and
clears ->status (in preparation for some future transaction).
The SMBus controller generates an INTR irq at the end of each
transaction where INTREN was set in the HST_CNT register.

No locking is needed around accesses to priv->status since all writes to
it are serialized: it is only ever set once in the isr at the end of a
transaction, and cleared while no interrupts can occur.  In addition, the
I2C adapter lock guarantees that entire I2C transactions for a single
adapter are always serialized.

For this patch, the INTREN bit is set only for SMBus block, byte and word
transactions, but not for I2C reads or writes.  The use of the DS
(BYTE_DONE) interrupt with byte-by-byte I2C transactions is implemented in
a subsequent patch.

The interrupt feature has only been enabled for COUGARPOINT hardware.
In addition, it is disabled if SMBus is using the SMI# interrupt.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

(Based on earlier work by Daniel Kurtz.)

Come up with a consistent, driver-wide strategy for event polling. For
intermediate steps of byte-by-byte block transactions, check for
BYTE_DONE or any error flag being set. At the end of every transaction
(regardless of PEC being used), check for both BUSY being cleared and
INTR or any error flag being set. This ensures proper action for all
transaction types.
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Cc: Daniel Kurtz <djkurtz@chromium.org>

Later patches enable interrupts.  This preliminary patch removes the older
unsupported ENABLE_INT9 flag.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Rename the SMBHSTCNT register bit access constants to match the style of
other register bits.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

If an error is detected in the polling loop, abort the transaction and
return an error code.

 * DEV_ERR is set if the device does not respond with an acknowledge, and
the SMBus controller times out (minimum 25ms).
 * BUS_ERR is set if a bus arbitration collision is detected.  In other
words, when the SMBus controller tries to generate a START condition, but
detects that the SMBDATA is being held low, usually by another SMBus/I2C
master.
 * FAILED is only set if a transaction is stopped by software (using
the SMBHSTCNT KILL bit).
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Writing back the whole status register could clear unwanted bits.
In particular, it could clear the "INUSE_STS" bit, which is a
'hardware semaphore', that might be useful to use some day.
To prepare for this, let's ban writing back the whole status to register
HST_STS, of which this is the only instance.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

As a slight optimization, pull some logic out of the polling loop during
byte-by-byte transactions by just setting the I801_LAST_BYTE bit, as
defined in the i801 (PCH) datasheet, when reading the last byte of a
byte-by-byte I2C_SMBUS_READ.
Signed-off-by: NDaniel Kurtz <djkurtz@chromium.org>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Some AMD chipsets, such as the SP5100, have an auxiliary SMBus
controller with a second set of registers. This patch adds
support for this auxiliary controller.

Tested on ASUS KCMA-D8 motherboard.
Signed-off-by: NAndrew Armenia <andrew@asquaredlabs.com>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Some chipsets have multiple sets of SMBus registers each controlling a
separate SMBus. Supporting these chipsets properly will require registering
multiple I2C adapters for one piix4.

The code to initialize and register the i2c_adapter structure has been
separated from piix4_probe and allows registration of a piix4 adapter
given its base address. Note that the i2c_adapter and i2c_piix4_adapdata
structures are now dynamically allocated.
Signed-off-by: NAndrew Armenia <andrew@asquaredlabs.com>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Some chipsets have multiple sets of piix4-compatible SMBus registers.
Eliminating the global variable will allow these chipsets to be fully
supported.

Return value from piix4_setup and piix4_sb800_setup now returns the smba
value detected. This is stored in a struct i2c_piix4_adapdata. Thus
the global variable is eliminated.
Signed-off-by: NAndrew Armenia <andrew@asquaredlabs.com>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Convert the drivers in drivers/i2c/busses/* to usemodule_pci_driver()
macro which makes the code smaller and a bit simpler.
Signed-off-by: NAxel Lin <axel.lin@gmail.com>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Signed-off-by: NJean Delvare <khali@linux-fr.org>
Cc: Rudolf Marek <r.marek@assembler.cz>
Cc: Olof Johansson <olof@lixom.net>
Cc: "Mark M. Hoffman" <mhoffman@lightlink.com>
Cc: Tomoya MORINAGA <tomoya.rohm@gmail.com>

My old e-mail address won't be valid for much longer. Time to update it.
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
Signed-off-by: NJean Delvare <khali@linux-fr.org>

Extends the driver to get properties from device tree. Rather than
pass the N & M factors in DT, use the more standard clock-frequency
property. Calculate N & M at run time. In order to do this, we need to
know tclk. So the driver uses clk_get() etc in order to get the clock
and clk_get_rate() to determine the tclk rate. Not all platforms
however have CLK, so some #ifdefery is needed to ensure the driver
still compiles when CLK is not available.
Signed-off-by: NAndrew Lunn <andrew@lunn.ch>

[wsa: converted some ints to u32 to match signedness]
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

There are three parts to this:

1) Remove the definitions of OCTEON_IRQ_TWSI and OCTEON_IRQ_TWSI2.
   The interrupts are specified by the device tree and these hard
   coded irq numbers block the used of the irq lines by the irq_domain
   code.

2) Remove platform device setup code from octeon-platform.c, it is
   now unused.

3) Convert i2c-octeon.c to use device tree.  Part of this includes
   using the devm_* functions instead of the raw counterparts, thus
   simplifying error handling.  No functionality is changed.
Signed-off-by: NDavid Daney <david.daney@cavium.com>
Acked-by: NRob Herring <rob.herring@calxeda.com>
Acked-by: NWolfram Sang <w.sang@pengutronix.de>
Cc: linux-mips@linux-mips.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/3939/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

With the changes in the random tree, IRQF_SAMPLE_RANDOM is now a
no-op; interrupt randomness is now collected unconditionally in a very
low-overhead fashion; see commit 775f4b29.  The IRQF_SAMPLE_RANDOM
flag was scheduled to be removed in 2009 on the
feature-removal-schedule, so this patch is preparation for the final
removal of this flag.
Signed-off-by: N"Theodore Ts'o" <tytso@mit.edu>
Cc: "Ben Dooks" <ben-linux@fluff.org>
Cc: "Wolfram Sang" <w.sang@pengutronix.de>

Allocate memory for device state using devm_kzalloc(), get the
clock using devm_clk_get(), get the IRQ using devm_request_irq(),
request and remap memory using devm_request_and_ioremap().
All to simplify accounting and letting the kernel do the
garbage-collection.
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Some architectures supports only 16-bit or 32-bit read/write access to
their IO space. Add a 'reg-io-width' platform and OF parameter which
specifies the IO width to support these platforms.

reg-io-width can be specified as 1, 2 or 4, and has a default value
of 1 if it is unspecified.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Deprecate 'regstep' property and use the standard 'reg-shift' property
for register offset shifts. 'regstep' will still be supported as an
optional property, but will give a warning when used.
Signed-off-by: NGanesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Cleanups to i2c-cores, no change in logic, changes are:
* Move i2c-ocores device tree documentation from source file to
  Documentation/devicetree/bindings/i2c/i2c-ocores.txt.
* Add \n to dev_warn and dev_err messages where missing
* Minor updates to the text and formatting fixes.
Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

As git history indicates, the driver predates the git era and is heavily
used and worked on since. Not EXPERIMENTAL anymore.
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>
Cc: Rodolfo Giometti <giometti@linux.it>
Cc: Florian Fainelli <ffainelli@freebox.fr>

There's no point in using _sync() as we don't really care if the suspend
has completed immediately.
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
Reviewed-by: NShubhrajyoti D <shubhrajyoti@ti.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

This commit fixes warning introduced in 27452498 ("i2c-s3c2410: Rework
device type handling"):

  drivers/i2c/busses/i2c-s3c2410.c: In function 's3c24xx_get_device_quirks':
  drivers/i2c/busses/i2c-s3c2410.c:125: warning: passing argument 1 of 'of_match_node' from incompatible pointer type
  include/linux/of.h:245: note: expected 'const struct of_device_id *' but argument is of type 'const struct of_device_id (*)[4]'
Signed-off-by: NKarol Lewandowski <k.lewandowsk@samsung.com>
Signed-off-by: NKyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

This patch configures the I2C bus timing registers according
to information passed via DT. Currently, 100kHz and 400kHz
modes are supported.

The TIMING2 register value is wrong in the documentation for
i.MX28! This was found and fixed by:
  Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: NMarek Vasut <marex@denx.de>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Now that u5500 is obsolete, u8500 is the only user of the Nomadik
i2c driver. As such there is no requirement to differentiate between
initialisation values. By the time a new SoC is released, almost all
of the ux500 platform will be DT:ed, so we can make decisions based
on the compatible property instead.
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NLee Jones <lee.jones@linaro.org>

Depend on 1e92bf6dSigned-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Depend on commit cf93feb3Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

TWI bit mask macros are moved to twi head file.
Depend on commit 61c16b5cSigned-off-by: NSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: NBob Liu <lliubbo@gmail.com>
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

Current driver was developed based on BF537 0.2 HRM. In high system load, BUFRDERR error
interrupt may be raised if XMTSERV interrupt of last TX byte is not served in time
(set RSTART bit), which breaks restart tranfer as expected.

"Buffer Read Error (BUFRDERR)" description in Blackfin HRM only applys to BF537
rev. < 0.3. In later rev. and later announced Blackfin chips, such as BF527 and
BF548, a new TWI master feature "Clock Stretching" is added into the TWI controller,
BUFRDERR interrupt is not triggered after TX FIFO is empty.

This patch sets RSTART bit at the beginning of the first transfer. The SCL and SDA
is hold till XMTSERV interrupt of last TX byte is served. Restart transfer is not broken
in high system load.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

[wsa: fixed spaces around operators]
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>

In order to mark I2C transfer fail when MEN bit in I2C controller is
reset unexpectedly in MCOMP interrupt, interrupt status bits XMTSERV or
RCVSERV should be checked.

Master Transfer Complete (MCOMP).
[1] The initiated master transfer has completed. In the absence of a
repeat start, the bus has been released.
[0] The completion of a transfer has not been detected.
Signed-off-by: NSonic Zhang <sonic.zhang@analog.com>

[wsa: fixed spaces around operators and typo in commit message]
Signed-off-by: NWolfram Sang <w.sang@pengutronix.de>