In particular, blend_setup() should not overwrite the other crtc's mixer
settings.  Also, the encoder needs to be able to specify the mixer-id
explicitly, since both LVDS and DTV use 'INTF_LVDC_DTV', so we cannot
guess the mixer-id from the interface.
Signed-off-by: NRob Clark <robdclark@gmail.com>

Downstream kernel IOMMU had a non-standard way of dealing with multiple
devices and multiple ports/contexts.  We don't need that on upstream
kernel, so rip out the crazy.

Note that we have to move the pinning of the ringbuffer to after the
IOMMU is attached.  No idea how that managed to work properly on the
downstream kernel.

For now, I am leaving the IOMMU port name stuff in place, to simplify
things for folks trying to backport latest drm/msm to device kernels.
Once we no longer have to care about pre-DT kernels, we can drop this
and instead backport upstream IOMMU driver.
Signed-off-by: NRob Clark <robdclark@gmail.com>

Signed-off-by: NRob Clark <robdclark@gmail.com>

Downstream kernel holds this clk via a fake-parent relationship.
Upstream clock framework requires that we hold it explicitly.
Signed-off-by: NRob Clark <robdclark@gmail.com>

Now that we (almost) have enough dependencies in place (MMCC, RPM, etc),
add necessary DT support so that we can use drm/msm on upstream kernel.

v2: update for review comments
v3: rebase on component helper changes
Signed-off-by: NRob Clark <robdclark@gmail.com>

The hw cursor is relatively adept at triggering underflows, which
manifest as a "blue flash" (since blue is configured as the underflow
color).  Juggle a few things around to tighten up the timing for setting
cursor registers in DONE irq.

And most importantly, don't ever disable the hw cursor.  Instead flip it
to a blank/empty cursor.  This seems far more reliable, as even simply
clearing the cursor-enable bit (with no other updates in previous/
following frames) can in some cases cause underflow.

v1: original
v2: add missing locking spotted by Micah

Cc: Micah Richert <richert@braincorporation.com>
Signed-off-by: NRob Clark <robdclark@gmail.com>

The HDMI block is basically the same between older SoC's with mdp4
display controller, and newer ones with mdp5.

So mostly this consists of better abstracting out the different sets of
regulators, clks, etc.  In particular, for regulators and clks we can
split it up by what is needed for hot plug detect to work, and what is
needed to light up the display.

Also, 8x74 has a new phy.. a very simple one, but split out into a
different mmio space.  And with mdp5, the irq is shared with mdp, so we
don't directly register our own irq handler.
Signed-off-by: NRob Clark <robdclark@gmail.com>

We'll want basically the same thing for mdp5, so refactor it out so it
can be shared.
Signed-off-by: NRob Clark <robdclark@gmail.com>

This can be shared between mdp4 and mdp5.  Both use the same set of
parameters to describe the format to the hw.
Signed-off-by: NRob Clark <robdclark@gmail.com>

There are some little bits and pieces that mdp4 and mdp5 can share, so
move things around so that we can have both in a common parent
directory.
Signed-off-by: NRob Clark <robdclark@gmail.com>

This adds the necessary configuration for the APQ8060A SoC (dual-core
krait + a320 gpu) as found on the bstem board.
Signed-off-by: NRob Clark <robdclark@gmail.com>

Add a VRAM carveout that is used for systems which do not have an IOMMU.

The VRAM carveout uses CMA.  The arch code must setup a CMA pool for the
device (preferrably in highmem.. a 256m-512m VRAM pool in lowmem is not
cool).  The user can configure the VRAM pool size using msm.vram module
param.

Technically, the abstraction of IOMMU behind msm_mmu is not strictly
needed, but it simplifies the GEM code a bit, and will be useful later
when I add support for a2xx devices with GPUMMU, so I decided to keep
this part.

It appears to be possible to configure the GPU to restrict access to
addresses within the VRAM pool, but this is not done yet.  So for now
the GPU will refuse to load if there is no sort of mmu.  Once address
based limits are supported and tested to confirm that we aren't giving
the GPU access to arbitrary memory, this restriction can be lifted
Signed-off-by: NRob Clark <robdclark@gmail.com>

There were a few potential problems with the original page_flip/vblank
code in mdp4_crtc.

1) We need vblank irq for a couple things, both completing flips and
   updating cursor.  We need to keep track of what work is pending so
   that (for example) a cursor update while we are still waiting for
   pageflip_cb (ie. pageflip requested from userspace, but still
   waiting for rendering to complete) would not prematurely trigger
   event to userspace.

2) A preclose -> pageflip-cancel should not cancel a pageflip that
   was requested on a different file (ie. non-master closing should
   not cancel a pending pageflip).

With these fixes, we no longer have problems w/ cursor not updating and
with occasional hangs with userspace waiting for a pageflip that had
been cancelled (launching XBMC from gnome-shell overview mode was a good
way to trigger this, but now works reliably).
Signed-off-by: NRob Clark <robdclark@gmail.com>

Enable using VG1 and VG2 for planes.  Currently YUV/CSC or scaling is
not enabled, but ARGB and xRGB blending is.
Signed-off-by: NRob Clark <robdclark@gmail.com>
Acked-by: NDavid Brown <davidb@codeaurora.org>

The include file has been removed and the file does not
need it anyway, so remove it. Fixes a compile error.
Signed-off-by: NJoerg Roedel <joro@8bytes.org>
Signed-off-by: NRob Clark <robdclark@gmail.com>

Drop the msm_connector base class, and special calls to base class
methods from the encoder, and use instead drm_bridge.  This allows for a
cleaner division between the hdmi (and in future dsi) blocks, from the
mdp block.
Signed-off-by: NRob Clark <robdclark@gmail.com>
Signed-off-by: NDave Airlie <airlied@redhat.com>

The snapdragon chips have multiple different display controllers,
depending on which chip variant/version.  (As far as I can tell, current
devices have either MDP3 or MDP4, and upcoming devices have MDSS.)  And
then external to the display controller are HDMI, DSI, etc. blocks which
may be shared across devices which have different display controller
blocks.

To more easily add support for different display controller blocks, the
display controller specific bits are split out into a "kms" module,
which provides the kms plane/crtc/encoder objects.

The external HDMI, DSI, etc. blocks are part encoder, and part connector
currently.  But I think I will pull in the drm_bridge patches from
chromeos tree, and split them into a bridge+connector, with the
registers that need to be set in modeset handled by the bridge.  This
would remove the 'msm_connector' base class.  But some things need to be
double checked to make sure I could get the correct ON/OFF sequencing..

This patch adds support for mdp4 crtc (including hw cursor), dtv encoder
(part of MDP4 block), and hdmi.
Signed-off-by: NRob Clark <robdclark@gmail.com>