1. 18 10月, 2017 1 次提交
  2. 17 10月, 2017 4 次提交
  3. 13 10月, 2017 1 次提交
  4. 11 10月, 2017 4 次提交
  5. 10 10月, 2017 2 次提交
  6. 07 10月, 2017 3 次提交
  7. 05 10月, 2017 2 次提交
  8. 29 9月, 2017 1 次提交
  9. 28 9月, 2017 1 次提交
  10. 26 9月, 2017 2 次提交
  11. 25 9月, 2017 2 次提交
  12. 22 9月, 2017 1 次提交
  13. 19 9月, 2017 1 次提交
  14. 15 9月, 2017 1 次提交
  15. 14 9月, 2017 3 次提交
    • Z
      drm/i915: Introduce private PAT management · 4395890a
      Zhi Wang 提交于
      The private PAT management is to support PPAT entry manipulation. Two
      APIs are introduced for dynamically managing PPAT entries: intel_ppat_get
      and intel_ppat_put.
      
      intel_ppat_get will search for an existing PPAT entry which perfectly
      matches the required PPAT value. If not, it will try to allocate a new
      entry if there is any available PPAT indexs, or return a partially
      matched PPAT entry if there is no available PPAT indexes.
      
      intel_ppat_put will put back the PPAT entry which comes from
      intel_ppat_get. If it's dynamically allocated, the reference count will
      be decreased. If the reference count turns into zero, the PPAT index is
      freed again.
      
      Besides, another two callbacks are introduced to support the private PAT
      management framework. One is ppat->update_hw(), which writes the PPAT
      configurations in ppat->entries into HW. Another one is ppat->match, which
      will return a score to show how two PPAT values match with each other.
      
      v17:
      
      - Refine the comparision of score of BDW. (Joonas)
      
      v16:
      
      - Fix a bug in PPAT match function of BDW. (Joonas)
      
      v15:
      
      - Refine some code flow. (Joonas)
      
      v12:
      
      - Fix a problem "not returning the entry of best score". (Zhenyu)
      
      v7:
      
      - Keep all the register writes unchanged in this patch. (Joonas)
      
      v6:
      
      - Address all comments from Chris:
      http://www.spinics.net/lists/intel-gfx/msg136850.html
      
      - Address all comments from Joonas:
      http://www.spinics.net/lists/intel-gfx/msg136845.html
      
      v5:
      
      - Add check and warnnings for those platforms which don't have PPAT.
      
      v3:
      
      - Introduce dirty bitmap for PPAT registers. (Chris)
      - Change the name of the pointer "dev_priv" to "i915". (Chris)
      - intel_ppat_{get, put} returns/takes a const intel_ppat_entry *. (Chris)
      
      v2:
      
      - API re-design. (Chris)
      Signed-off-by: NZhi Wang <zhi.a.wang@intel.com>
      Cc: Ben Widawsky <benjamin.widawsky@intel.com>
      Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> #v7
      Reviewed-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      [Joonas: Use BIT() in the enum in bdw_private_pat_match]
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/1505392783-4084-1-git-send-email-zhi.a.wang@intel.com
      4395890a
    • J
      drm/i915: Introduce INTEL_GEN_MASK · fe52e597
      Joonas Lahtinen 提交于
      Split INTEL_GEN_MASK out of IS_GEN macro, and make it usable
      within static declarations (unlike compound statements).
      
      v2:
      - s/combound/compound/ (Tvrtko)
      - Fix whitespace (yes, we need automatic checkpatch.pl)
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Reviewed-by: NJani Nikula <jani.nikula@intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20170913115255.13851-1-joonas.lahtinen@linux.intel.com
      fe52e597
    • C
      drm/i915/execlists: Read the context-status HEAD from the HWSP · 767a983a
      Chris Wilson 提交于
      The engine also provides a mirror of the CSB write pointer in the HWSP,
      but not of our read pointer. To take advantage of this we need to
      remember where we read up to on the last interrupt and continue off from
      there. This poses a problem following a reset, as we don't know where
      the hw will start writing from, and due to the use of power contexts we
      cannot perform that query during the reset itself. So we continue the
      current modus operandi of delaying the first read of the context-status
      read/write pointers until after the first interrupt. With this we should
      now have eliminated all uncached mmio reads in handling the
      context-status interrupt, though we still have the uncached mmio writes
      for submitting new work, and many uncached mmio reads in the global
      interrupt handler itself. Still a step in the right direction towards
      reducing our resubmit latency, although it appears lost in the noise!
      
      v2: Cannonlake moved the CSB write index
      v3: Include the sw/hwsp state in debugfs/i915_engine_info
      v4: Also revert to using CSB mmio for GVT-g
      v5: Prevent the compiler reloading tail (Mika)
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Michel Thierry <michel.thierry@intel.com>
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@intel.com>
      Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
      Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
      Cc: Zhi Wang <zhi.a.wang@intel.com>
      Acked-by: NMichel Thierry <michel.thierry@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20170913085605.18299-6-chris@chris-wilson.co.ukReviewed-by: NMika Kuoppala <mika.kuoppala@intel.com>
      767a983a
  16. 13 9月, 2017 1 次提交
  17. 12 9月, 2017 5 次提交
  18. 08 9月, 2017 1 次提交
  19. 07 9月, 2017 4 次提交