- 25 2月, 2012 1 次提交
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由 Tony Lindgren 提交于
There's no need to have these defines in plat/io.h. Note that we now need to ifdef omap_read/write calls as they will be available for omap1 only. While at it, clean up the includes to group them like they typically are grouped. Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 17 12月, 2011 1 次提交
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由 Santosh Shilimkar 提交于
Local timer clock is sourced from the CPU clock and hence changes along with CPU clock. These per CPU local timers are used as clock-events, so they need to be reconfigured on CPU frequency change as part of CPUfreq governor. Newly introduced clockevents_reconfigure() needs to know the twd clock-rate. Provide a clock-node to make clk_get_rate() work for TWD. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> [paul@pwsan.com: renamed clock node to 'mpu_periphclk' to indicate that this is the Cortex-A9 MPCore subsystem clock PERIPHCLK (DDI 0407G); moved clock and clkdev entries to match the autogenerated script output] Signed-off-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 16 12月, 2011 1 次提交
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由 Keshava Munegowda 提交于
device name usbhs clocks are changed from usbhs-omap.0 to usbhs_omap; this is because in the hwmod registration the device name is set as usbhs_omap; The redudant clock nodes are removed. Signed-off-by: NKeshava Munegowda <keshava_mgowda@ti.com> Reviewed-by: NPartha Basak <parthab@india.ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 05 11月, 2011 1 次提交
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由 Benoit Cousson 提交于
The commit 318c3e15 added some "fck" clock alias to timer devices that are not needed anymore since hwmod framework will create them automatically. A warning was added to highlight and thus fix the redundancy. [ 0.616424] omap_timer.1: alias fck already exists [ 0.621948] omap_timer.2: alias fck already exists [ 0.627380] omap_timer.3: alias fck already exists [ 0.632781] omap_timer.4: alias fck already exists [ 0.638214] omap_timer.5: alias fck already exists [ 0.643615] omap_timer.6: alias fck already exists [ 0.649078] omap_timer.7: alias fck already exists [ 0.654479] omap_timer.8: alias fck already exists [ 0.659881] omap_timer.9: alias fck already exists [ 0.665283] omap_timer.10: alias fck already exists [ 0.670776] omap_timer.11: alias fck already exists Remove all the clkdev entries for timer fck alias. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Tarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 07 10月, 2011 3 次提交
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由 Jon Hunter 提交于
The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the parent clock of the AESS_FCLK is the ABE_FCLK... ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which determine their operational frequency. However, the dividers for the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit, which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2. Similarly, when this bit is set to 1, the AESS_FCLK divider is 2 and the OCP_ABE_ICLK is 1. The above relationship between the AESS_FCLK and OCP_ABE_ICLK dividers ensure that the OCP_ABE_ICLK clock is always half the frequency of the ABE_CLK... OCP_ABE_ICLK = ABE_FCLK/2 The divider for the OCP_ABE_ICLK is currently missing so add a divider that will ensure the OCP_ABE_ICLK frequency is always half the ABE_FCLK frequency. Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Paul Walmsley 提交于
OMAP4460 specific clocks are not getting added as the cpu_is_omap44xx is choosing only OMAP4430 specific clock nodes. Changing it to add to OMAP4460 specific clocks also. This is clocks are required of temperature sensor. Signed-off-by: NVishwanath BS <vishwanath.bs@ti.com> Signed-off-by: NKeerthy <j-keerthy@ti.com> Cc: paul@pwsan.com [paul@pwsan.com: updated to apply] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Mike Turquette 提交于
OMAP4 DPLL_ABE can enable a 4X multipler on top of the normal MN multipler and divider. This is achieved by setting CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit in CKGEN module of CM1. From the OMAP4 TRM: Fdpll = Fref x 2 x (4 x M/(N+1)) in case REGM4XEN bit field is set (only applicable to DPLL_ABE). Add new round_rate() and recalc() functions for OMAP4, that check the setting of REGM4XEN bit and handle this appropriately. The new functions are a simple wrapper on top of the existing omap2_dpll_round_rate() and omap2_dpll_get_rate() functions to handle the REGM4XEN bit. The REGM4XEN bit is only implemented for the ABE DPLL on OMAP4 and so only dpll_abe_ck uses omap4_dpll_regm4xen_round_rate() and omap4_dpll_regm4xen_recalc() functions. Signed-off-by: NMike Turquette <mturquette@ti.com> Tested-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NJon Hunter <jon-hunter@ti.com> [paul@pwsan.com: fixed attempt to return a negative from a fn returning unsigned; pass along errors from omap2_dpll_round_rate(); added documentation; added Jon's S-o-b] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 22 9月, 2011 1 次提交
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由 Tarun Kanti DebBarma 提交于
Add device name to OMAP2 dmtimer fclk nodes so that the fclk nodes can be retrieved by doing a clk_get with the corresponding device pointers or device names. Reviewed-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: NTarun Kanti DebBarma <tarun.kanti@ti.com> Signed-off-by: NThara Gopinath <thara@ti.com> Acked-by: NCousson, Benoit <b-cousson@ti.com> [tony@atomide.com: fixed typo in email address] Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 21 8月, 2011 1 次提交
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由 Paul Walmsley 提交于
Fix the following compile warning: arch/arm/mach-omap2/clock44xx_data.c: In function 'omap4xxx_clk_init': arch/arm/mach-omap2/clock44xx_data.c:3371:6: warning: 'cpu_clkflg' may be used uninitialized in this function The approach taken here is intended to work if omap4xxx_clk_init() is converted into an initcall. Thanks to Bjarne Steinsbo <bsteinsbo@gmail.com> for proposing another approach. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Bjarne Steinsbo <bsteinsbo@gmail.com>
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- 20 8月, 2011 1 次提交
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由 Paul Walmsley 提交于
After commit 665d0013 ("OMAP2+: hwmod: Follow the recommended PRCM module enable sequence"), device drivers for OMAP IP blocks that do not use runtime PM can cause oopses or kernel instability[1][2]. This is because those non-runtime PM drivers do not use the hwmod code, which implements the correct IP block enable and disable sequence. Several options for dealing with this problem have been proposed: 1. Add a new field to the OMAP struct clk to mark clocks that are currently used by non-runtime PM drivers. Modify the clock code to use the old clockdomain sequence for these marked clocks. As drivers are converted to use runtime PM, remove the annotation from the clocks. 2. Similar to #1, but associate the flag with the struct omap_clk instead. 3. Add IDLEST wait support to the OMAP4 clock code, similar to the way it is implemented for OMAP2/3, and enable it in each struct clk currently used by non-runtime PM drivers. As drivers are converted to use runtime PM, remove the annotation from the clocks. 4. Do nothing; leave the problem to those responsible for the unconverted drivers. 5. Re-enable clock-based clockdomain control in the OMAP4 clock code. This would revert back to the behavior of Linux 3.0, simply with a slightly longer module enable/disable latency. Unfortunately, no approach seemed particularly good. Options 1 through 3 seemed unwise due to the following reasons: A. The OMAP struct clks are intended primarily to describe hardware clock nodes, and the intention is that no driver-specific data should be stored there (applies to #1) B. The resulting patch would have been quite large for the -rc series (applies to #1, #2, #3) C. The patch would have been a new, yet temporary hack; and similar fixes have drawn negative comments in the recent past (see for example [3]) Option 4 is undesirable because commit 665d0013 ("OMAP2+: hwmod: Follow the recommended PRCM module enable sequence") has resulted in a less stable kernel; and kernel stability is more important than OMAP4 power management. Option 5 is the approach taken in this patch. This seemed to be the least intrusive approach for 3.1-rc. The approach in this patch was originally proposed by Ohad Ben-Cohen <ohad@wizery.com>. I'm simply writing the commit message and passing it along. ... Thanks to Luciano Coelho <coelho@ti.com> for reporting the problem. Thanks to Ohad Ben-Cohen <ohad@wizery.com> for tracking the problem down, generating a temporary workaround, and proposing a patch to deal with the problem. Thanks to Rajendra Nayak <rnayak@ti.com> for proposing another patch to deal with the problem. Thanks to Felipe Balbi <balbi@ti.com> for comments. 1. Coelho, Luciano <coelho@ti.com>. _Re: Oops on ehci_hcd when booting 3.0.0-rc2 on panda_. Tue, 09 Aug 2011 14:26:08 +0300. Posted to the <linux-omap@vger.kernel.org> mailing list. Available from (among others) http://www.spinics.net/linux/lists/linux-omap/msg55213.html 2. Munegowda, Keshava <keshava_mgowda@ti.com>. _Re: Oops on ehci_hcd when booting 3.0.0-rc2 on panda_. Thu, 11 Aug 2011 13:51:05 +0530. Posted to the <linux-omap@vger.kernel.org> mailing list. Available from (among others) http://www.spinics.net/linux/lists/linux-omap/msg55371.html 3. King, Russell <linux@arm.linux.org.uk>. _Re: [PATCH 5/8] OMAP4: PM: TEMP: Prevent l3init from idling/force sleep_. Thu, 23 Jun 2011 16:22:49 +0100. Posted to the <linux-omap@vger.kernel.org> mailing list. Available from (among others) http://www.mail-archive.com/linux-omap@vger.kernel.org/msg51392.htmlSigned-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Luciano Coelho <coelho@ti.com> Cc: Ohad Ben-Cohen <ohad@wizery.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com>
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- 10 7月, 2011 11 次提交
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由 Rajendra Nayak 提交于
On OMAP4, the PRCM recommended sequence for enabling a module after power-on-reset is: -1- Force clkdm to SW_WKUP -2- Enabling the clocks -3- Configure desired module mode to "enable" or "auto" -4- Wait for the desired module idle status to be FUNC -5- Program clkdm in HW_AUTO(if supported) This sequence applies to all older OMAPs' as well, however since they use autodeps, it makes sure that no clkdm is in IDLE, and hence not requiring a force SW_WKUP when a module is being enabled. OMAP4 does not need to support autodeps, because of the dyanamic dependency feature, wherein the HW takes care of waking up a clockdomain from idle and hence the module, whenever an interconnect access happens to the given module. Implementing the sequence for OMAP4 requires the clockdomain handling that is currently done in clock framework to be done as part of hwmod framework since the step -4- above to "Wait for the desired module idle status to be FUNC" is done as part of hwmod framework. Signed-off-by: NRajendra Nayak <rnayak@ti.com> [b-cousson@ti.com: Adapt it to the new clkdm hwmod attribute and API] Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped mach-omap2/clock.c changes; modified to only call the clockdomain code if oh->clkdm is set; disable clock->clockdomain interaction on OMAP4] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Rajendra Nayak 提交于
On OMAP4 the auxclk nodes (part of SCRM) support both divider as well as parent selection. Supporting this requires splitting the existing nodes (which support only parent selection) into two nodes, one for parent and another for divider selection. The nodes for parent selection are named auxclk*_src_ck and the ones for divider selection as auxclk*_ck. Signed-off-by: NRajendra Nayak <rnayak@ti.com> [b-cousson@ti.com: Rebase on top of clock cleanup and autogen alignement] Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Benoit Cousson 提交于
Extend the existing function to create clkdev for every optional clocks to add a well one "fck" alias for the main_clk of the omap_hwmod. It will allow to remove these static clkdev entries from the clockXXX_data.c file. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Todd Poynor <toddpoynor@google.com> [paul@pwsan.com: remove all of the "fck" role clkdev aliases from the clock data files; fixed error message] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Santosh Shilimkar 提交于
On OMAP4, CPU accesses on unmapped addresses are redirected to GPMC by L3 interconnect. Because of CPU speculative nature, such accesses are possible which can lead to indirect access to GPMC and if it's clock is not running, it can result in hang/abort on the platform. Above makes access to GPMC unpredictable during the execution, so it's module mode needs to be kept under hardware control instead of software control. Since the auto gating is supported for GPMC, there isn't any power impact because of this change. The issue was un-covered with security middleware running along with HLOS. In this case GPMC had a valid MMU descriptor on secure side where as HLOS didn't map the GMPC because it isn't being used. Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> [b-cousson@ti.com: Update subject and fix typos in the changelog] Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Kevin Hilman <khilman@ti.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Tomi Valkeinen 提交于
Add missing DSS optional clocks to HWMOD data for OMAP4xxx. Add HWMOD_CONTROL_OPT_CLKS_IN_RESET flag for dispc to fix dispc reset. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> [b-cousson@ti.com: Remove a comment and update the subject] Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> [paul@pwsan.com: removed DSS "fck" role and some clkdev aliases at Tomi's request] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jon Hunter 提交于
UNIPRO was removed from OMAP4 devices from ES2.0 onwards. Since this IP was anyway non-functional and not supported, it is best to remove it completely. Signed-off-by: NJon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the changelog] Signed-off-by: NBenoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM header file changes into a separate patch] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jon Hunter 提交于
McASP2, 3 and MMC6 modules are not present in the OMAP4 family. Remove the fclk and the clksel related to these nodes. Rename the references that were potentially re-used in order nodes. Remove related macros in prcm header files. Update TI copyright date. Signed-off-by: NJon Hunter <jon-hunter@ti.com> [b-cousson@ti.com: Update the patch according to autogen output] Signed-off-by: NBenoit Cousson <b-cousson@ti.com> [paul@pwsan.com: split PRCM data changes into a separate patch] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Benoit Cousson 提交于
The DPLL USB can generate higher speed (x2) than the regular ones. The max multiplication value is then twice the previous value. Fix both max_mult and max_div with that correct values. Change the max_div variable type to u16 to allow storing up to 256. Replace as well the define with the value to avoid unneeded indirection and provide a better readability. Remove the defines that become useless. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Benoit Cousson 提交于
A couple of fieds were edited manually and thus do not stick to the template used by the generator and by other structures. Move them to the correct location. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped the UNIPRO changes since those will be removed in a later patch] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Benoit Cousson 提交于
usb_host_fs_fck does have a clkdev mapping with "usbhs-omap.0" and "fs_fck" alias used by the driver. The entry with NULL dev is thus not needed anymore. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Benoit Cousson 提交于
The USB DPLL is a J-Type DPLL with the sddiv extra parameter. Add it in USB DPLL. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Cc: Paul Walmsley <paul@pwsan.com> [paul@pwsan.com: dropped UNIPRO change since it is removed in a later patch] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 08 7月, 2011 1 次提交
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由 Rajendra Nayak 提交于
Add the new clock nodes (bandgap_ts_fclk, div_ts_ck) for omap4460. Handle these nodes using the clock flags (CK_*). Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NNishanth Menon <nm@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Reviewed-by: NKevin Hilman <khilman@ti.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 21 4月, 2011 1 次提交
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由 Tomi Valkeinen 提交于
DSS driver has used fck and ick clocks on OMAP2/3 to get DSS HW up and running, and also to get the pixel clock's source clock rate from the fck. On OMAP4 the clock data is set up in a different way, as there's no ick, dss_fck points to a fake clock which just affects DSS's MODULEMODE, and dss_dss_clk if the DSS_FCK. >From DSS driver's point of view the dss_fck sounds like an ick, and dss_dss_clk is the fck. While this is not entirely correct from HW point of view, especially for the ick, configuring the clock aliases that way makes DSS "just work" with OMAP4's clock setup. In the (hopefully near) future DSS driver will be reworked to use pm_runtime support which should clean up the clock code. Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Cc: Benoît Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 11 3月, 2011 2 次提交
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由 Sumit Semwal 提交于
DSS code uses ick as one of the clocks in clk_get/clk_put. OMAP4 clock database doesn't have ick for DSS, so adding ick as dummy clock. This is needed for backward compatibility with OMAP2/3. Once pm_runtime* APIs get introduced in DSS, this will be revisited. Signed-off-by: NSumit Semwal <sumit.semwal@ti.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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由 Sumit Semwal 提交于
Currently, clock database has <dev, clock-name> tuples for DSS2. Because of this, the clock names are different across different OMAP platforms. This patch aligns the DSS2 clock names and roles across OMAP 2420, 2430, 3xxx, 44xx platforms in the clock databases, hwmod databases for opt-clocks, and DSS clock handling. This ensures that clk_get/put/enable/disable APIs in DSS can use uniform role names. Signed-off-by: NSumit Semwal <sumit.semwal@ti.com> Acked-by: NPaul Walmsley <paul@pwsan.com> Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com>
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- 02 3月, 2011 1 次提交
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由 Kishore Kadiyala 提交于
Modifying the device & driver name from "mmci-omap-hs" to "omap_hsmmc". Signed-off-by: NKishore Kadiyala <kishore.kadiyala@ti.com> Acked-by: Benoit Cousson<b-cousson@ti.com> Signed-off-by: NTony Lindgren <tony@atomide.com>
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- 01 3月, 2011 1 次提交
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由 Keshava Munegowda 提交于
The devices of clocks are set to usbhs, so that only usbhs common driver can invoke these clocks. The dummy per port clocks are added to omap3 clock data base. This helps to invoke common clock get APIs for omap3 and omap4. Signed-off-by: NKeshava Munegowda <keshava_mgowda@ti.com> Signed-off-by: NFelipe Balbi <balbi@ti.com>
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- 26 2月, 2011 3 次提交
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由 Paul Walmsley 提交于
Disable autoidle on all clocks during clock framework initialization. (If CONFIG_PM is set, autoidle is re-enabled for all clocks later in the boot process.) The principle behind this patch, and some similar patches, is that the kernel should start with all power management features disabled. Later in the boot process, the PM code, if compiled in with CONFIG_PM, enables or re-enables power management features. Signed-off-by: NPaul Walmsley <paul@pwsan.com> Tested-by: NRajendra Nayak <rnayak@ti.com> Reviewed-by: NKevin Hilman <khilman@ti.com>
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由 Rajendra Nayak 提交于
Enable hardware gate control for all dpll MX and X2 postdividers. This requires the allow_idle/deny_idle functions to be populated for all clock nodes (mx/x2 post dividers) in clkops. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Rajendra Nayak 提交于
All OMAP3/4 dpll's support hardware level autogating. Populate allow_idle/deny_idle function pointers for all DPLL's in clkops. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 19 1月, 2011 1 次提交
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由 Felipe Balbi 提交于
A few headers are included twice, remove them. Found the following errors using make includecheck: arch/arm/mach-omap2/clock44xx_data.c: prm44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm1_44xx.h is included more than once. arch/arm/mach-omap2/clockdomains44xx_data.c: cm2_44xx.h is included more than once. arch/arm/mach-omap2/powerdomain2xxx_3xxx.c: prm-regbits-34xx.h is included more than once. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: NFelipe Balbi <balbi@ti.com> [paul@pwsan.com: dropped lists from patch cc:s; tweaked subject line] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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- 23 12月, 2010 1 次提交
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由 Jon Hunter 提交于
The following OMAP4 clocks have the following fixed divisors that determine the frequency at which these clocks operate. These dividers are defined by the PRCM specification and without these dividers the rates of the below clocks are calculated incorrectly. This may cause internal peripherals using these clocks to operate at the wrong frequency. - abe_24m_fclk (freq = divided-by-8) - ddrphy_ck (freq = parent divided-by-2) - dll_clk_div_ck (freq = parent divided-by-2) - per_hs_clk_div_ck (freq = parent divided-by-2) - usb_hs_clk_div_ck (freq = parent divided-by-3) - func_12m_fclk (freq = parent divided-by-16) - func_24m_clk (freq = parent divided-by-4) - func_24mc_fclk (freq = parent divided-by-8) - func_48mc_fclk (freq = divided-by-4) - lp_clk_div_ck (freq = divided-by-16) - per_abe_24m_fclk (freq = divided-by-4) Signed-off-by: NJon Hunter <jon-hunter@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Kevin Hilman <khilman@deeprootsystems.com> Cc: Rajendra Nayak <rnayak@ti.com>
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- 22 12月, 2010 8 次提交
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由 Santosh Shilimkar 提交于
L3INSTR clock domain is read only register and its reset value is HW_AUTO. The modules withing this clock domain needs to be kept under hardware control. MODULEMODE: - 0x0: Module is disable by software. Any INTRCONN access to module results in an error, except if resulting from a module wakeup (asynchronous wakeup). - 0x1: Module is managed automatically by hardware according to clock domain transition. A clock domain sleep transition put module into idle. A wakeup domain transition put it back into function. If CLKTRCTRL=3, any INTRCONN access to module is always granted. Module clocks may be gated according to the clock domain state. This patch keeps CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL and CM_L3INSTR_INTRCONN_WP1_CLKCTRL module mode under hardware control by using ENABLE_ON_INIT flag. Without this the OMAP4 device OFF mode SAR restore phase aborts during interconnect register restore phase. This can be also handled by doing explicit a clock enable and disable in the low power code since there is no direct module associated with it. But that seems not necessary since the clock domain is under HW control. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NBenoit Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Hari Kanigeri 提交于
In omap4, there is no explicit configuration register to enable mailbox clocks. Defining dummy clock for mailbox clock module to keep the mailbox driver backward compatible with previous omaps. Signed-off-by: NHari Kanigeri <h-kanigeri2@ti.com> Acked-by: NBenoît Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jon Hunter 提交于
J-Type DPLLs have additional configuration parameters that need to be programmed when setting the multipler and divider for the DPLL. These parameters being the sigma delta divider (SD_DIV) for the DPLL and the digital controlled oscillator (DCO) to be used by the DPLL. The current code is implemented specifically to configure the OMAP3630 PER J-Type DPLL. The OMAP4430 USB DPLL is also a J-Type DPLL and so this code needs to be updated to work for both OMAP3 and OMAP4 devices and any other future devices that have J-TYPE DPLLs. For the OMAP3630 PER DPLL both the SD_DIV and DCO paramenters are used but for the OMAP4430 USB DPLL only the SD_DIV field is used. The current implementation will only program the SD_DIV and DCO fields if the DPLL has both and hence this does not work for OMAP4430. In order to make the code more generic add two new fields to the dpll_data structure for the SD_DIV field and DCO field bit-masks and only program these fields if the masks are defined for a specific DPLL. This simplifies the code and allows us to remove the flag DPLL_NO_DCO_SEL. Tested on OMAP36xx Zoom3 and OMAP4 Blaze. Signed-off-by: NJon Hunter <jon-hunter@ti.com> [paul@pwsan.com: removed explicit inlining and added '_' prefix on lookup_*() functions; added testing info to commit message; added 35xx comments back in] Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Benoit Cousson 提交于
Fix opt clocks name in clock framework and hwmod. Add the missing iclk in the ocp_if structure. Add the HWMOD_CONTROL_OPT_CLKS_IN_RESET flag to ensure the the GPIO optional clock is enable during reset. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Tested-by: NCharulatha V <charu@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
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由 Rajendra Nayak 提交于
The CORE and PER M3 post dividers are different from the rest of the DPLL post dividers as in they go to SCRM, and are used there to export clocks for instance used by external sensor. There is no automatic HW dependency in PRCM to manage them. Hence these two clocks (dpll post dividers) should be managed by SW and explicitly enabled/disabled. Add control in clock framework to handle that. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Rajendra Nayak 提交于
Add support for auxiliary clocks nodes which are part of SCRM. Signed-off-by: NRajendra Nayak <rnayak@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com>
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由 Jonathan Bergsagel 提交于
Add register address, mask and link to the clksel structure that were missing in the IVA DPLL mux clock node. Signed-off-by: NJonathan Bergsagel <jbergsagel@ti.com> Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
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由 Thara Gopinath 提交于
This patch extends the OMAP4 clock data to include various x2 clock nodes between DPLL and HS dividers as the clock framework skips a x2 while calculating the dpll locked frequency. The clock database extensions are autogenerated using the scripts maintained by Benoit Cousson. Signed-off-by: NBenoit Cousson <b-cousson@ti.com> Signed-off-by: NThara Gopinath <thara@ti.com> [paul@pwsan.com: fixed merge conflicts against v2.6.37-rc5; dropped dpll_mpu_x2_ck on advice from Benoît] Signed-off-by: NPaul Walmsley <paul@pwsan.com> Cc: Rajendra Nayak <rnayak@ti.com>
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