1. 12 3月, 2012 4 次提交
  2. 06 3月, 2012 2 次提交
  3. 25 2月, 2012 4 次提交
  4. 23 2月, 2012 3 次提交
  5. 22 2月, 2012 2 次提交
  6. 10 2月, 2012 1 次提交
  7. 06 2月, 2012 7 次提交
  8. 21 1月, 2012 3 次提交
  9. 05 1月, 2012 1 次提交
  10. 19 12月, 2011 1 次提交
  11. 09 12月, 2011 3 次提交
    • J
      ARM: OMAP1: Always reprogram dpll1 rate at boot · c116abc4
      Janusz Krzysztofik 提交于
      DPLL1 reprogramming to a different rate is actually blocked inside
      omap1_select_table_rate(). However, it is already forced at boot, for
      boards which boot at unusable clock rates, and this seems to work
      correctly.
      
      OTOH, we now have a fine, run time performed clock selection algorithm
      implemented, which prevents less powerfull SoCs from being overclocked
      unintentionally.
      
      Allow reprogramming of dpll1 by default, and use it for switching to the
      higest supported clock rate with all boards, including those already
      booting at a usable rate of 60 MHz or above.
      
      Created against linux-omap/master tip as of Thu Dec 1,
      commit f83c2a8cbb59981722d1ab610c79adfd034a2667. Requires the just
      submitted patch "ARM: OMAP1: Move dpll1 rates selection from config to
      runtime" to prevent from unintentional overclocking. Tested on Amstrad
      Delta.
      Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      c116abc4
    • J
      ARM: OMAP1: Update dpll1 default rate reprogramming method · f9e5908f
      Janusz Krzysztofik 提交于
      According to comments in omap1_select_table_rate(), reprogramming dpll1
      is tricky, and should always be done from SRAM.
      
      While being at it, move OMAP730 special case handling inside
      omap_sram_reprogram_clock().
      
      Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1
      reprogramming related issues", which it depends on.
      Tested on Amstrad Delta.
      Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      f9e5908f
    • J
      ARM: OMAP1: Move dpll1 rates selection from config to runtime · 24ce2705
      Janusz Krzysztofik 提交于
      For still better multi-OMAP1 support, expand omap1_rate_table with flags
      for different SoC types and match them while selecting clock rates. The
      idea is stolen from current omap24xx clock rate selection algorithm.
      
      Since clkdev platform flag definitions are reused here, those had to be
      expanded with one extra entry for OMAP1710 subtype, as this is the only
      SoC for which we allow selection of the highest, 216 MHz rate.
      
      Once done, remove no longer needed clock rate configure time options.
      
      Tested on Amstrad Delta.
      Signed-off-by: NJanusz Krzysztofik <jkrzyszt@tis.icnet.pl>
      [tony@atomide.com: updated comments]
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      24ce2705
  12. 06 12月, 2011 1 次提交
  13. 02 12月, 2011 2 次提交
  14. 27 11月, 2011 1 次提交
  15. 19 11月, 2011 1 次提交
  16. 18 11月, 2011 1 次提交
  17. 12 11月, 2011 1 次提交
    • T
      ARM: OMAP: Fix reprogramming of dpll1 rate · e9b7086b
      Tony Lindgren 提交于
      Commit a66cb345 (ARM: OMAP: Map SRAM
      later on with ioremap_exec()) moved the SRAM init to happen later
      to remove a dependency to early SoC detection for map_io.
      
      This broke booting on some boards not using Kconfig option for
      OMAP_CLOCKS_SET_BY_BOOTLOADER as the dpll1 reprogramming would
      cause the following error:
      
      kernel BUG at arch/arm/plat-omap/sram.c:226!
      Internal error: Oops - undefined instruction: 0 [#1] PREEMPT
      Modules linked in:
      
      CPU: 0    Not tainted  (3.2.0-rc1-e3 #9)
      PC is at omap_sram_reprogram_clock+0x28/0x30
      LR is at omap1_select_table_rate+0x88/0xb4
      pc : [<c001b0c4>]    lr : [<c0019f54>]    psr: 600000d3
      sp : c035bf10  ip : c035bf20  fp : c035bf1c
      r10: c035bfd4  r9 : 54029252  r8 : c03f8120
      r7 : c0362b50  r6 : 00b71b00  r5 : c03873cc  r4 : c0362b40
      r3 : 00000000  r2 : c0362b40  r1 : 0000010a  r0 : 00002cb0
      Flags: nZCv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
      Control: 0000317f  Table: 10004000  DAC: 00000017
      Process swapper (pid: 0, stack limit = 0xc035a270)
      Stack: (0xc035bf10 to 0xc035c000)
      bf00:                                     c035bf3c c035bf20 c0019f54 c001b0ac
      bf20: 00001000 00002cb3 00000004 c035ed4c c035bf74 c035bf40 c033ea24 c0019edc
      bf40: c02f526c 00000002 00000015 bc058c9b 93111a16 c035335c 02000000 c035ed4c
      bf60: c035ed4c c03f8120 c035bf84 c035bf78 c00194c4 c033e8ec c035bfc4 c035bf88
      bf80: c033bc24 c00194a0 c035bf90 c035bf98 00000000 00000000 00000000 00000000
      bfa0: 00000001 00000000 c0354678 c035ece4 10004000 103532f4 c035bff4 c035bfc8
      bfc0: c0338574 c033b598 00000000 00000000 00000000 c035467c 0000317d c035c03c
      bfe0: c0354678 c035ece4 00000000 c035bff8 10008040 c0338508 00000000 00000000
      Backtrace:
      [<c001b09c>] (omap_sram_reprogram_clock+0x0/0x30) from [<c0019f54>] (omap1_select_table_rate+0x88/0xb4)
      [<c0019ecc>] (omap1_select_table_rate+0x0/0xb4) from [<c033ea24>] (omap1_clk_init+0x148/0x334)
       r7:c035ed4c r6:00000004 r5:00002cb3 r4:00001000
      [<c033e8dc>] (omap1_clk_init+0x0/0x334) from [<c00194c4>] (omap1_init_early+0x34/0x48)
       r8:c03f8120 r7:c035ed4c r6:c035ed4c r5:02000000 r4:c035335c
      [<c0019490>] (omap1_init_early+0x0/0x48) from [<c033bc24>] (setup_arch+0x69c/0x79c)
      [<c033b588>] (setup_arch+0x0/0x79c) from [<c0338574>] (start_kernel+0x7c/0x2f4)
      [<c03384f8>] (start_kernel+0x0/0x2f4) from [<10008040>] (0x10008040)
       r7:c035ece4 r6:c0354678 r5:c035c03c r4:0000317d
      Code: 0a000002 e1a0e00f e12fff13 e89da800 (e7f001f2)
      
      Fix this by adding omap1_clk_late_init() that only reprograms dpll1
      if the bootloader rate is less than 60MHz. This also allows removing
      of the OMAP_CLOCKS_SET_BY_BOOTLOADER option.
      Reported-by: NAaro Koskinen <aaro.koskinen@iki.fi>
      Tested-by: NAaro Koskinen <aaro.koskinen@iki.fi>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      e9b7086b
  18. 10 11月, 2011 1 次提交
  19. 05 11月, 2011 1 次提交