- 03 3月, 2015 11 次提交
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由 Laurent Pinchart 提交于
The atomic page flip helper implements the page flip operation using asynchronous commits. As the legacy page flip was the last CRTC operation that needed direct access to plane setup, the plane setup functions can now become private to the plane implementation. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The atomic connector DPMS helper implements the connector DPMS operation using atomic commit, removing the need for DPMS helper operations on CRTCs and encoders. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
This removes the legacy mode config code. The CRTC and encoder prepare and commit operations are not used anymore, remove them. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
When using atomic updates the CRTC .enable() and .disable() helper operations are preferred over the (then legacy) .prepare() and .commit() operations. Implement .enable() and rework .disable() to not depend on DPMS, easing DPMS removal later on. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Hook up the default .reset(), .atomic_duplicate_state() and .atomic_free_state() helpers to ensure that state objects are properly created and destroyed, and call drm_mode_config_reset() at init time to create the initial state objects. Framebuffer reference count also gets maintained automatically by the transitional helpers except for the legacy page flip operation. Maintain it explicitly there. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Use the new CRTC atomic transitional helpers drm_helper_crtc_mode_set() and drm_helper_crtc_mode_set_base() to implement the CRTC .mode_set and .mode_set_base operations. This delegates primary plane configuration to the plane .atomic_update and .atomic_disable operations, removing duplicate code from the CRTC implementation. There is now no code path available to the driver in which to drop the reference to the CRTC acquired in the .prepare() operation if an error then occurs. The driver thus now leaks a reference if an error occurs during mode set. So be it, this will be fixed in a further step of the atomic update transition. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Implement the CRTC .atomic_begin() and .atomic_flush() operations, the plane .atomic_check(), .atomic_update() and operations, and use the transitional atomic helpers to implement the plane update and disable operations on top of the new atomic operations. The plane setup code can't be moved out of the CRTC start function completely yet, as the atomic code paths are not taken every time the CRTC needs to be started. This results in some code duplication that will be fixed after switching to atomic updates completely. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Explicitly create the CRTC primary plane instead of relying on the core helpers to do so. This simplifies the plane logic by merging the KMS and software planes. Reject plane API operations on the primary planes for now, as that code will anyway be refactored when implementing support for atomic updates. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The DRM core vblank handling mechanism requires drivers to forcefully turn vblank reporting off when disabling the CRTC, and to restore the vblank reporting status when enabling the CRTC. Implement this using the drm_crtc_vblank_on/off helpers. When disabling vblank we must first wait for page flips to complete, so implement page flip completion wait as well. Finally, drm_crtc_vblank_off() must be called at startup to synchronize the state of the vblank core code with the hardware, which is initially disabled. This is performed at CRTC creation time, requiring vertical blanking to be initialized before creating CRTCs. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Turning a CRTC off will prevent a queued page flip from ever completing, potentially confusing userspace. Wait for queued page flips to complete before turning the CRTC off to avoid this. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The next commit will need functions to be reordered to avoid forward declarations. Do it separately to help review. This only moves functions without any change to the code. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- 23 12月, 2014 5 次提交
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由 Laurent Pinchart 提交于
Accept interlaced modes on the VGA and HDMI connectors and configure the hardware accordingly. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The intermediate DPMS standby and suspend states are a thing from the past. They only matter in practice for VGA CRT monitors, and are just a power saving vs. resume time optimization. Given that they have never been implemented properly in the rcar-du driver and that the Intel driver has dropped them on the vga port years ago, it's safe to only care about the on and off states. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The DU outputs by default a composite sync signal (XOR of the horizontal and vertical sync signals) on the HSYNC output pin. As this can confuse devices and isn't needed by any of the supported encoders, configure the HSYNC pin to output the horizontal sync signal. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The DU uses the module functional clock as the default pixel clock, but supports using an externally supplied pixel clock instead. Support this by adding the external pixel clock to the DT bindings, and selecting the clock automatically at runtime based on the requested mode pixel frequency. The input clock pins to DU channels routing is configurable, but currently hardcoded to connect input clock i to channel i. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Rename the feature from RCAR_DU_FEATURE_DEFR8 to RCAR_DU_FEATURE_EXT_CTRL_REGS to cover all extended control registers in addition to the DEFR8 register. Usage of the feature is refactored to optimize runtime operation and prepare for external clock support. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- 27 11月, 2014 1 次提交
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由 Julia Lawall 提交于
Propagate the error code on failure. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ identifier ret; expression e1,e2; @@ ( if (\(ret < 0\|ret != 0\)) { ... return ret; } | ret = 0 ) ... when != ret = e1 when != &ret *if(...) { ... when != ret = e2 when forall return ret; } // </smpl> Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- 05 11月, 2014 1 次提交
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由 Daniel Vetter 提交于
Just a bit of OCD cleanup on headers - this function isn't the core interface any more but just a helper for drivers who haven't yet transitioned to universal planes. Put the declaration at the right spot and sprinkle necessary #includes over all drivers. Maybe this helps to encourage driver maintainers to do the switch. v2: Fix #include ordering for tegra, reported by 0-day builder. v3: Include required headers, reported by Thierry. Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Thierry Reding <treding@nvidia.com> Reviewed-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NSean Paul <seanpaul@chromium.org> Signed-off-by: NDaniel Vetter <daniel.vetter@intel.com>
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- 15 9月, 2014 1 次提交
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由 Laurent Pinchart 提交于
The "Renesas Corporation" listed in the copyright notice doesn't exist. Replace it with "Renesas Electronics Corporation" and update the copyright years. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- 02 4月, 2014 1 次提交
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由 Matt Roper 提交于
Now that CRTC's have a primary plane, there's no need to track the framebuffer in the CRTC. Replace all references to the CRTC fb with the primary plane's fb. This patch was generated by the Coccinelle semantic patching tool using the following rules: @@ struct drm_crtc C; @@ - (C).fb + C.primary->fb @@ struct drm_crtc *C; @@ - (C)->fb + C->primary->fb v3: Generate patch via coccinelle. Actual removal of crtc->fb has been moved to a subsequent patch. v2: Fixup several lingering crtc->fb instances that were missed in the first patch iteration. [Rob Clark] Signed-off-by: NMatt Roper <matthew.d.roper@intel.com> Reviewed-by: NRob Clark <robdclark@gmail.com>
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- 02 12月, 2013 2 次提交
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由 Laurent Pinchart 提交于
When setting a new frame buffer with the mode set base operation the pitch value might change. Set the hardware plane pitch register at the same time as the plane base address in the rcar_du_plane_update_base() function to make sure the pitch value always matches the frame buffer. Cc: stable@vger.kernel.org Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Reuse the previously cast variable instead. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- 30 8月, 2013 1 次提交
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由 Keith Packard 提交于
This lets drivers see the flags requested by the application [airlied: fixup for rcar/imx/msm] Signed-off-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NDave Airlie <airlied@gmail.com>
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- 10 8月, 2013 8 次提交
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由 Laurent Pinchart 提交于
The R8A7790 includes two internal LVDS encoders. Support them in the DU driver. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The R8A7790 DU variant has a single RGB output called DPAD0 that can be fed with the output of DU0, DU1 or DU2. Making the routing configurable. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Split the output routing specification between SoC-internal data, specified in the rcar_du_device_info structure, and board data, passed through platform data. The DU has 5 possible outputs (DPAD0/1, LVDS0/1, TCON). SoC-internal output routing data specify which output are valid, which CRTCs can be connected to the valid outputs, and the type of in-SoC encoder for the output. Platform data then specifies external encoders and the output they are connected to. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The R8A7790 DU has 3 CRTCs, split in two groups. Support them. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Output routing is configured in group registers, move the corresponding code from rcar_du_crtc.c to rcar_du_group.c. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending unit, timings generator, ...) and device-global resources (start/stop control, planes, ...) shared between the two CRTCs. The R8A7790 introduced a third CRTC with its own set of global resources This would be modeled as two separate DU device instances if it wasn't for a handful or resources that are shared between the three CRTCs (mostly related to input and output routing). For this reason the R8A7790 DU must be modeled as a single device with three CRTCs, two sets of "semi-global" resources, and a few device-global resources. Introduce a new rcar_du_group driver-specific object, without any real counterpart in the DU documentation, that models those semi-global resources. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Create a single rcar_du_encoder structure that implements a KMS encoder. The current implementation is straightforward and only configures CRTC output routing. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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由 Laurent Pinchart 提交于
Some of the DU revisions use one clock and IRQ per CRTC instead of one clock and IRQ per device. Retrieve the correct clock and register the correct IRQ for each CRTC. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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- 27 6月, 2013 1 次提交
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由 Laurent Pinchart 提交于
The R-Car Display Unit (DU) DRM driver supports both superposition processors and all eight planes in RGB and YUV formats with alpha blending. Only VGA and LVDS encoders and connectors are currently supported. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NDave Airlie <airlied@redhat.com>
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