1. 15 4月, 2013 2 次提交
  2. 25 9月, 2010 1 次提交
    • M
      x86, mem: Optimize memmove for small size and unaligned cases · 3b4b682b
      Ma Ling 提交于
      movs instruction will combine data to accelerate moving data,
      however we need to concern two cases about it.
      
      1. movs instruction need long lantency to startup,
         so here we use general mov instruction to copy data.
      2. movs instruction is not good for unaligned case,
         even if src offset is 0x10, dest offset is 0x0,
         we avoid and handle the case by general mov instruction.
      Signed-off-by: NMa Ling <ling.ma@intel.com>
      LKML-Reference: <1284664360-6138-1-git-send-email-ling.ma@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      3b4b682b
  3. 24 8月, 2010 2 次提交
    • M
      x86, mem: Optimize memcpy by avoiding memory false dependece · 59daa706
      Ma Ling 提交于
      All read operations after allocation stage can run speculatively,
      all write operation will run in program order, and if addresses are
      different read may run before older write operation, otherwise wait
      until write commit. However CPU don't check each address bit,
      so read could fail to recognize different address even they
      are in different page.For example if rsi is 0xf004, rdi is 0xe008,
      in following operation there will generate big performance latency.
      1. movq (%rsi),	%rax
      2. movq %rax,	(%rdi)
      3. movq 8(%rsi), %rax
      4. movq %rax,	8(%rdi)
      
      If %rsi and rdi were in really the same meory page, there are TRUE
      read-after-write dependence because instruction 2 write 0x008 and
      instruction 3 read 0x00c, the two address are overlap partially.
      Actually there are in different page and no any issues,
      but without checking each address bit CPU could think they are
      in the same page, and instruction 3 have to wait for instruction 2
      to write data into cache from write buffer, then load data from cache,
      the cost time read spent is equal to mfence instruction. We may avoid it by
      tuning operation sequence as follow.
      
      1. movq 8(%rsi), %rax
      2. movq %rax,	8(%rdi)
      3. movq (%rsi),	%rax
      4. movq %rax,	(%rdi)
      
      Instruction 3 read 0x004, instruction 2 write address 0x010, no any
      dependence.  At last on Core2 we gain 1.83x speedup compared with
      original instruction sequence.  In this patch we first handle small
      size(less 20bytes), then jump to different copy mode. Based on our
      micro-benchmark small bytes from 1 to 127 bytes, we got up to 2X
      improvement, and up to 1.5X improvement for 1024 bytes on Corei7.  (We
      use our micro-benchmark, and will do further test according to your
      requirment)
      Signed-off-by: NMa Ling <ling.ma@intel.com>
      LKML-Reference: <1277753065-18610-1-git-send-email-ling.ma@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@zytor.com>
      59daa706
    • M
      x86, mem: Don't implement forward memmove() as memcpy() · fdf42896
      Ma, Ling 提交于
      memmove() allow source and destination address to be overlap, but
      there is no such limitation for memcpy().  Therefore, explicitly
      implement memmove() in both the forwards and backward directions, to
      give us the ability to optimize memcpy().
      Signed-off-by: NMa Ling <ling.ma@intel.com>
      LKML-Reference: <C10D3FB0CD45994C8A51FEC1227CE22F0E483AD86A@shsmsx502.ccr.corp.intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      fdf42896
  4. 17 4月, 2008 1 次提交
  5. 30 1月, 2008 1 次提交
  6. 11 10月, 2007 2 次提交
  7. 01 7月, 2006 1 次提交
  8. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4