- 31 7月, 2014 23 次提交
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由 Rafał Miłecki 提交于
This reverts commit d7a887a7. Function add_temporary_entry is needed by bcm47xx to support highmem. We need to add a temporary entry to check for amount of RAM. The only change made in this revert was replacing (ENTER|EXIT)_CRITICAL. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7395/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Rafał Miłecki 提交于
Detect more devices and register leds & buttons for them. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7394/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Rafał Miłecki 提交于
It seems that bcm47xx can handle only 128 MiB of RAM directly. There are few devices with 256 MiB, but Broadcom's SDK uses highmem to handle anything above 128 MiB. Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7101/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Rafał Miłecki 提交于
Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7100/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Rafał Miłecki 提交于
Reported-by: NCatalin Patulea <cat@vv.carleton.ca> Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Acked-by: NHauke Mehrtens <hauke@hauke-m.de> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7113/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Rafał Miłecki 提交于
Catalin reported that GPIOs used by bcm47xx don't match layout of his WRT54GS V1.0 board. It seems we need to distinguish these 54G* devices. Reported-by: NCatalin Patulea <cat@vv.carleton.ca> Signed-off-by: NRafał Miłecki <zajec5@gmail.com> Cc: linux-mips@linux-mips.org Cc: Hauke Mehrtens <hauke@hauke-m.de> Patchwork: https://patchwork.linux-mips.org/patch/7112/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
Since this CONFIG option will be used for both Loongson-3A/3B machines, and not all Loongson-3 machines are produced by Lemote, we rename CONFIG_LEMOTE_MACH3A to CONFIG_LOONGSON_MACH3X. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7190/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
Loongson-3 has some specific instructions (MMI/SIMD) in coprocessor 2. COP2 isn't independent because it share COP1 (FPU)'s registers. This patch enable the COP2 usage so user-space programs can use the MMI/SIMD instructions. When COP2 exception happens, we enable both COP1 (FPU) and COP2, only in this way the fp context can be saved and restored correctly. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7189/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
Loongson-3B is a 8-cores processor. In general it looks like there are two Loongson-3A integrated in one chip: 8 cores are separated into two groups (two NUMA node), each node has its own local memory. Of course there are some differences between one Loongson-3B and two Loongson-3A. E.g., the base addresses of IPI registers of each node are not the same; Loongson-3A use ChipConfig register to enable/disable clock, but Loongson-3B use FreqControl register instead. There are two revision of Loongson-3B, the first revision is called as Loongson-3B1000, whose frequency is 1GHz and has a PRid 0x6306, the second revision is called as Loongson-3B1500, whose frequency is 1.5GHz and has a PRid 0x6307. Both revisions has a bug that clock cannot be disabled at runtime, but this will be fixed in future. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7188/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
Enable sys_mbind()/sys_get_mempolicy()/sys_set_mempolicy() for O32, N32, and N64 ABIs. By the way, O32/N32 should use the compat version of sys_migrate_pages()/sys_move_pages(), so fix that. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7186/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
Multiple Loongson-3A chips can be interconnected with HT0-bus. This is a CC-NUMA system that every chip (node) has its own local memory and cache coherency is maintained by hardware. The 64-bit physical memory address format is as follows: 0x-0000-YZZZ-ZZZZ-ZZZZ The high 16 bits should be 0, which means the real physical address supported by Loongson-3 is 48-bit. The "Y" bits is the base address of each node, which can be also considered as the node-id. The "Z" bits is the address offset within a node, which means every node has a 44 bits address space. Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally, because many other MIPS CPUs have also extended their address spaces. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7187/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
This patch is prepared for Multi-chip interconnection. Since each chip has a ChipConfig register, LOONGSON_CHIPCFG should be an array. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7185/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
This patch is prepared for Loongson's NUMA support, it offer meaningful sysfs files such as physical_package_id, core_id, core_siblings and thread_siblings in /sys/devices/system/cpu/cpu?/topology. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Reviewed-by: NAndreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7184/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Huacai Chen 提交于
On MIPS currently, only the soft limit of cpu count (maxcpus) has its effect, this patch enable the hard limit (nr_cpus) as well. Processor cores which greater than maxcpus and less than nr_cpus can be taken up via cpu hotplug. The code is borrowed from X86. Signed-off-by: NHuacai Chen <chenhc@lemote.com> Reviewed-by: NAndreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7183/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Emil Goode 提交于
We check that the struct vm_area_struct pointer vma is NULL and then dereference it a few lines below. The intent was to make sure vma is not NULL but this is not necessary since the bug pre-dates GIT history and seem to never have caused a problem. The tlb-4k and tlb-8k versions of local_flush_tlb_page() don't bother checking if vma is NULL, also vma is dereferenced before being passed to local_flush_tlb_page(), thus it is safe to remove this NULL check. Signed-off-by: NEmil Goode <emilgoode@gmail.com> Reviewed-by: NJonas Gorski <jogo@openwrt.org> Acked-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: Paul Gortmaker <paul.gortmaker@windriver.com> Cc: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: kernel-janitors@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7264/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
The dma_cache_wback_inv function performs exactly as is required here, unless the system has coherent I/O in which case it's a no-op. Call the underlying cache writeback functions directly, which is arguably clearer anyway given that the code doesn't actually have anything to do with DMA in a strict sense. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7282/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
When determining the VPE ID of a CPU, make use of the cpu_vpe_id macro which will return 0 in a non-MT kernel build. Most code is already doing so but a couple of places weren't. Fixing this prevents a build failure for non-MT kernels where struct cpuinfo_mips does not contain the vpe_id field: arch/mips/kernel/pm-cps.c: In function 'cps_pm_enter_state': arch/mips/kernel/pm-cps.c:153:51: error: 'struct cpuinfo_mips' has no member named 'vpe_id' vpe_cfg = &core_cfg->vpe_config[current_cpu_data.vpe_id]; arch/mips/kernel/smp-cps.c: In function 'wait_for_sibling_halt': arch/mips/kernel/smp-cps.c:363:33: error: 'struct cpuinfo_mips' has no member named 'vpe_id' unsigned vpe_id = cpu_data[cpu].vpe_id; Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
When used in a non-MT kernel, the cpu_vpe_id macro never made use of its cpuinfo argument. It doesn't actually need to since it is returning a constant 0. However not using the argument can lead to build failures if the compiler then notices that a variable used as part of the argument is unused. Prevent that problem by "using" the argument as far as the compiler is concerned, whilst still returning 0 as before. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7280/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
The pm-cps code can run without a CPC, although will be limited to using only the 2 wait idle states. However the code does check for CPC presence, and in order to work optimally the CPC support is needed. So select it. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7279/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Paul Burton 提交于
These symbols will not be defined when CONFIG_MIPS_CPS=n, but although the CPS_PM_POWER_GATED state will never be used in that case the compiler doesn't have enough information to figure that out. Add checks which evaluate to a constant false for CONFIG_MIPS_CPS=n cases in order to help the compiler out & eliminate the symbol references. Signed-off-by: NPaul Burton <paul.burton@imgtec.com> Reviewed-by: NMarkos Chandras <markos.chandras@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7278/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Hauke Mehrtens 提交于
This patch adds detection for the Microsoft MN-700 and the Asus WL500G router. This is based on some old code from OpenWrt. Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Cc: zajec5@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7490/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Hauke Mehrtens 提交于
The address prefix 00:90:4C is used by Broadcom in their initial configuration. When a mac address with the prefix 00:90:4C is used all devices from the same series are sharing the same mac address. To prevent mac address collisions we replace them with a mac address based on the base address. To generate such addresses we take the main mac address from et0macaddr and increase it by two for the first wifi device and by 3 for the second one. This matches the printed mac address on the device. The main mac address increased by one is used as wan address by the vendor code. Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Cc: zajec5@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7489/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Hauke Mehrtens 提交于
The reboot on the BCM47XX SoCs is done, by setting the watchdog counter to 1 and let it trigger a reboot, when it reaches 0. Some devices with a BCM4705/BCM4785 SoC do not reboot when the counter is set to 1 and decreased to 0 by the hardware. It looks like it works more reliable when we set it to 3. As far as I understand the hardware, this should not make any difference, but I do not have access to any documentation for this SoC. It is still not 100% reliable. Signed-off-by: NHauke Mehrtens <hauke@hauke-m.de> Cc: zajec5@gmail.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7488/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 7月, 2014 17 次提交
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由 Atsushi Nemoto 提交于
Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7216/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
This pci fixup routine calls __init functions. In general pci fixup routine must not call __init functions, but this pci/isa bridge device is not hotpluggable anyway. Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7215/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Atsushi Nemoto 提交于
Fix wrong code spotted by -Werror=array-bounds: arch/mips/txx9/generic/pci.c:334:23: error: array subscript is above array bounds [-Werror=array-bounds] pci_write_config_byte(dev, regs[i], dat); Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7214/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
This fixes a regression caused by commit bb6c0bd3 [MIPS: SB1: Fix excessive kernel warnings.], that makes `-march=r5000' selected for compilation flags rather than supposed `-march=sb1' with compilers that do not support the ASE selection flags introduced with that change. For example GCC 4.1.2 supports `-mips3d'/`-mno-mips3d' (and obviously `-march=sb1'), however it does not support `-mdmx'/`-mno-mdmx'. As a result the whole selection of flags fails and compilation resorts to using `-march=r5000', meant for really old compilers indeed only. It is always best to pick the flags individually unless we are absolutely sure a set of flags was introduced to the toolchain together (`-march=sb1' and `-mtune=sb1' would be a good example), and this change makes it happen for CONFIG_CPU_SB1. Consequently the flags ultimately selected with GCC 4.1.2 are `-march=sb1 -Wa,--trap -mno-mips3d' Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: Richard Sandiford <rdsandiford@googlemail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7223/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
This fixes: {standard input}: Assembler messages: {standard input}:145: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2' {standard input}:920: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$9' {standard input}:1797: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:1851: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:2831: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:4209: Error: opcode not supported on this processor: vr5000 (mips4) `clz $7,$7' {standard input}:4329: Error: opcode not supported on this processor: vr5000 (mips4) `clz $2,$2' make[2]: *** [arch/mips/mm/tlbex.o] Error 1 which triggered due to a regression causing the file to be built with `-march=r5000' rather than `-march=sb1', fixed separately. Nevertheless the error should not happen, the other uses of CLZ are appropriately guarded. This change copies the arrangement from one of those other places. Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7222/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Maciej W. Rozycki 提交于
Code in a switch statement in probe_pcache checks the CPU type twice unnecessarily for processor implementations that have the alias removal feature reported by the CP0 Config7.AR and Config7.IAR bits. This change rewrites the affected fragment avoiding the extraneous check and improving readability. Signed-off-by: NMaciej W. Rozycki <macro@linux-mips.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7221/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Wire up the set_affinity call for the internal PIC if booting on a cpu supporting it. Affinity is kept to boot cpu as default. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7323/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
In preparation for applying affinity, use the irq descriptor as the argument for (un)mask. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7317/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7322/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Since we will have the chance of accessing the registers concurrently, protect any accesses through a spinlock. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7321/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7320/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Set it to zero if there is no second set. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7319/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
The SMP capable irq controllers have two interrupt output pins which are controlled through separate registers, so make the variables arrays. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7318/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
The generic version uses a variable length of u32 registers instead of u32/u64. This allows easier support for "wider" registers without having to rewrite everything. This "generic" version is as fast as the old version in the best case (i == next set bit), and twice as fast in the worst case in 64 bits. Using a macro was chosen over a (forced) inline version because gcc generated more compact code with the macro. The change from (signed) int to unsigned int for i and to_call was intentional as the value can be only between 0 and (width - 1) anyway, and allowed gcc to optimise the code a bit further. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7316/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Allows up to drop the prototypes from the top. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7315/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Make it follow the same naming convention as the other functions. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Cc: Gregory Fong <gregory.0xf0@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7314/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Jonas Gorski 提交于
Use the same pattern as with get_*_cpu_type() to allow the compiler to remove code for non enabled SoC types. Signed-off-by: NJonas Gorski <jogo@openwrt.org> Cc: linux-mips@linux-mips.org Cc: John Crispin <blogic@openwrt.org> Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7273/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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