We no longer have users for these functions so they can be removed.
Remove also unused enums from the header file.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

In case when the interrupt happened for the second eDMA the channel
number was incorrectly passed to the client driver.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
CC: <stable@vger.kernel.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

When stopping a DMA transfer with interrupts disabled it is possible
that the DMA transfer completes before the events are cleared. In
this case the completion interrupt will be pending, causing a
completion callback after the transfer was stopped.

By clearing the completion interrupt for the stopping channel it is
ensured that no completion event will be generated after the stop.
Signed-off-by: NJohn Ogness <john.ogness@linutronix.de>
Acked-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>

The recently introduced resume hook in the edma driver
is not referenced when CONFIG_PM_SLEEP is not set, which
results in a compile warning in keystone builds.

This adds an appropriate #ifdef.

Cc: Nishanth Menon <nm@ti.com>
Cc: Daniel Mack <zonque@gmail.com>
Cc: Joel Fernandes <joelf@ti.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Fixes: a2b11751: ("ARM: common: edma: add suspend resume hook")
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch makes the edma driver resume correctly after suspend. Tested
on an AM33xx platform with cyclic audio streams and omap_hsmmc.

All information can be reconstructed by already known runtime
information.

As we now use some functions that were previously only used from __init
context, annotations had to be dropped.

[nm@ti.com: added error handling for runtime + suspend_late/early_resume]
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NDaniel Mack <zonque@gmail.com>
Tested-by: NJoel Fernandes <joelf@ti.com>
Acked-by: NJoel Fernandes <joelf@ti.com>
[nsekhar@ti.com: remove unneeded pm_runtime_get_sync() from resume]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The horrible split between the low-level part of the edma support
and the dmaengine front-end driver causes problems on multiplatform
kernels. This is an attempt to improve the situation slightly
by only registering the dmaengine devices that are actually
present.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
[olof: add missing include of linux/dma-mapping.h]
Signed-off-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The edma_setup_from_hw() should know about the CC number when parsing the
CCCFG register - when it reads the register to be precise. The base
addresses for CCs stored in an array and we need to provide the correct id
to edma_read() in order to read the correct register.

Cc: <stable@vger.kernel.org> # 3.16
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

In some cases it is desired to move a channel to a specific event queue.
Such a use case is audio, where it is preferred that it is served with
highest priority compared to other DMA clients.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Use the lowest priority queue as default for clients.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

From CCCFG register of eDMA3 we can get all the needed information for the
driver about the IP:
Number of channels: NUM_DMACH
Number of regions: NUM_REGN
Number of slots (PaRAM sets): NUM_PAENTRY
Number of TC/EQ: NUM_EVQUE

In case when booted with DT or the queue_priority_mapping is not provided
set up a default priority map.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

To be consistent in the code that we take parameters from edma_cc[j] struct
and not randomly from info[j] as well.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The struct edma is allocated per CC bases so the member num_cc does not make
any sense. One CC is one CC, it does not have sub CCs.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

There is no need to change the default TC -> Queue mapping. By default the
mapping is: TC0 -> Q0, TC1 -> Q1, etc.
Changing this has no benefits at all and all the board files are just setting
the same mapping back to the HW.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Instead of saving the for loop length, take the num_tc value from the pdata.
In case of DT boot set the n_tc to 3 as it is hardwired in edma_of_parse_dt()
This is a temporary state since upcoming patch(es) will change how we are
dealing with these parameters.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The pdata has been just allocated with devm_kzalloc() in
edma_setup_info_from_dt() and passed to this function.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Get the two interrupt line number at the same time by merging the two
instance of if(node){}else{} places.
replace the &pdev->dev with the already existing dev which makes it possible
to collapse lines with devm_request_irq()
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

As Joel pointed out, edma_read_position() uses memcpy_fromio() to read
the parameter ram. That's not synchronized with the internal update as
it does a byte by byte copy. We need to do a 32bit read to get a
consistent value.

Further reading destination and source is pointless. In DEV_TO_MEM
transfers we are only interested in the destination, in MEM_TO_DEV we
care about the source. In MEM_TO_MEM it really does not matter which
one you read.

Simple solution: Remove the pointers, select dest/source via a bool
and return the read value.

Remove the export of this function while at it. The only potential
user is the dmaengine and that's always builtin.
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

This is another great example of trainwreck engineering:

commit 2646a0e529 (ARM: edma: Add EDMA crossbar event mux support)
added support for using EDMA on peripherals which have no direct EDMA
event mapping.

The code compiles and does not explode in your face, but that's it.

1) Reading an u16 array from an u32 device tree array simply does not
   work. Even if the function is named "edma_of_read_u32_to_s16_array".

   It merily calls of_property_read_u16_array. So the resulting 16bit
   array will have every other entry = 0.

2) The DT entry for the xbar registers related to xbar has length 0x10
   instead of the real length: 0xfd0 - 0xf90 = 0x40.

   Not a real problem as it does not cross a page boundary, but
   wrong nevertheless.

3) But none of this matters as the mapping never happens:

   After reading nonsense edma_of_read_u32_to_s16_array() invalidates
   the first array entry pair, so nobody can ever notice the
   braindamage by immediate explosion.

Seems the QA criteria for this code was solely not to explode when
someone adds edma-xbar-event-map entries to the DT. Goal achieved,
congratulations!

Not really helpful if someone wants to use edma on a device which
requires a xbar mapping.

Fix the issues by:

- annotating the device tree entry with "/bits/ 16" as documented in
  the of_property_read_u16_array kernel doc

- make the size of the xbar register mapping correct

- invalidating the end of the array and not the start

This convoluted mess wants to be completely rewritten as there is no
point to keep the xbar_chan array memory and the iomapping of the xbar
regs around forever. Marking the xbar mapped channels as used should
be done right there.

But that's a different issue and this patch is small enough to make it
work and allows a simple backport for stable.

Cc: stable@vger.kernel.org # v3.12+
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Indicate that the edma dmaengine driver has support for cyclic mode.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: NJoel Fernandes <joelf@ti.com>
Reviewed-and-Tested-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

For later use save the number of queues available for the CC.
Signed-off-by: NPeter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: NJoel Fernandes <joelf@ti.com>
Reviewed-and-Tested-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

edma header defines DMA_COMPLETE, this causes issues as commit adfedd9a move
DMA_SUCCESS to DMA_COMPLETE. edma should properly namespace its defines and
needs a future fix
Reported-by: NOlof Johansson <olof@lixom.net>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

HWMOD removal for MMC is breaking edma_start as the events are being manually
triggered due to unused channel list not being clear.

The above issue is fixed by reading the "dmas" property from the DT node if it
exists and clearing the bits in the unused channel list if the dma controller
used by any device is EDMA. For this purpose we use the of_* helpers to parse
the arguments in the dmas phandle list.

Also introduced is a minor clean up of a checkpatch error in old code.
Reviewed-by: NSekhar Nori <nsekhar@ti.com>
Reported-by: NBalaji T K <balajitk@ti.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Olof Johansson <olof@lixom.net>
Cc: Nishanth Menon <nm@ti.com>
Cc: Pantel Antoniou <panto@antoniou-consulting.com>
Cc: Jason Kridner <jkridner@beagleboard.org>
Cc: Koen Kooi <koen@dominion.thruhere.net>
Signed-off-by: NJoel Fernandes <joelf@ti.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Manual trigger for events missed as a result of splitting a
scatter gather list and DMA'ing it in batches. Add a helper
function to trigger a channel incase any such events are missed.
Signed-off-by: NJoel Fernandes <joelf@ti.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Remove duplicated include.
Signed-off-by: NWei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

EDMA supports a cross bar which provides ability
to mux additional events into physical channels
present in the channel controller.

This is required when the number of events present
in the system are more than number of available
physical channels.

Changes by Joel:
* Split EDMA xbar support out of original EDMA DT parsing patch
to keep it easier for review.
* Rewrite shift and offset calculation.
Suggested-by: NSekhar Nori <nsekhar@ti.com>
Suggested by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: NJoel A Fernandes <joelagnel@ti.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
[nsekhar@ti.com: fix checkpatch errors and a minor coding improvement]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Adds support for parsing the TI EDMA DT data into the required EDMA
private API platform data. Enables runtime PM support to initialize
the EDMA hwmod. Enables build on OMAP.

Changes by Joel:
* Setup default one-to-one mapping for queue_priority and queue_tc
mapping as discussed in [1].
* Split out xbar stuff to separate patch. [1]
* Dropped unused DT helper to convert to array
* Fixed dangling pointer issue with Sekhar's changes

[1] https://patchwork.kernel.org/patch/2226761/Signed-off-by: NMatt Porter <mporter@ti.com>
[nsekhar@ti.com: fix checkpatch errors, build breakages. Introduce
edma_setup_info_from_dt() as part of that effort]
Signed-off-by: NJoel A Fernandes <joelagnel@ti.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Use devm_ioremap_resource instead of reques_mem_region()/ioremap(),
devm_request_irq() instead of request_irq() and kzalloc() calls to
devm_kzalloc().

This ensures more consistent error values and simplifies error paths.
Signed-off-by: NLad, Prabhakar <prabhakar.csengg@gmail.com>
[nsekhar@ti.com: add missing err.h include]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Fix build on OMAP, the irqs are undefined on AM33xx.
These error interrupt handlers were hardcoded as disabled
so since they are unused code, simply remove them.
Signed-off-by: NMatt Porter <mporter@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Move mach-davinci/dma.c to common/edma.c so it can be used
by OMAP (specifically AM33xx) as well.
Signed-off-by: NMatt Porter <mporter@ti.com>
Acked-by: Chris Ball <cjb@laptop.org> # davinci_mmc.c
Acked-by: NMark Brown <broonie@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
[nsekhar@ti.com: dropped davinci sffsdr changes]
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

This adds additional error checking to the private edma api implementation
to catch the case where the edma_alloc_slot() has an invalid controller
parameter. The edma dmaengine wrapper driver relies on this condition
being handled in order to avoid setting up a second edma dmaengine
instance on DA830.

Verfied using a DA850 with the second EDMA controller platform instance
removed to simulate a DA830 which only has a single EDMA controller.
Reported-by: NTomas Novotny <tomas@novotny.cz>
Signed-off-by: NMatt Porter <mporter@ti.com>
Cc: stable@vger.kernel.org # v3.7.x+
Tested-by: NTomas Novotny <tomas@novotny.cz>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Use for_each_set_bit_from to iterate over all the set bit in a memory
region.
Signed-off-by: NAkinobu Mita <akinobu.mita@gmail.com>
Acked-by: NSekhar Nori <nsekhar@ti.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Christian Riesch <christian.riesch@omicron.at>
Cc: Kevin Hilman <khilman@ti.com>
Cc: davinci-linux-open-source@linux.davincidsp.com
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

The ISR does quiete a lot of hw access which could be avoided. First it
checks for a pending interrupt by reading alteast one register. Then it
checks for the "activated" slots by reading another register. This is
more or a less a must.
Now, once it found an active slot it does the same two reads again.
After that it "knows" that there must be a pending transfer however it
cross checks with the other register. There are 32 bit in an interger
which are polled instead of considering only the set bits and ignoring
those which are zero. This performs atleast 32 reads which could be
avoided. In case of a first match it does another read.
This patch reorganizes the access by re-using the register which have
been read and then uses ffs() to find the matching slot instead looping
over it. By doing this we get rid of the last (32 + 2 + hits) reads.

It is possible however that by really busy bank0 we never get to handle
bank1. If this is a problem, we could try to handle bank1 after we are
done with bank0 to check if there are any outstanding transfers.

To put some numbers on this, this is from spi transfer via spidev. The
first column is the number of total transfers, the time stamp is taken
before and after the ioctl():

|10000, min: 542us      avg: 591us
|20000, min: 542us      avg: 592us
|30000, min: 542us      avg: 592us
|40000, min: 542us      avg: 585us
|50000, min: 542us      avg: 593us

The same test case with the patch applied
|10000, min: 444us      avg: 493us
|20000, min: 444us      avg: 491us
|30000, min: 444us      avg: 489us
|40000, min: 444us      avg: 491us
|50000, min: 444us      avg: 492us

that is almost 100us that just went away.
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Default queue is expected to be a low-priority queue.
This way, long transfers on the default queue started
by the codec engine will not cause audio defects.
Signed-off-by: NHeiko Schocher <hs@denx.de>
Signed-off-by: NJuha Kuikka <juha.kuikka@gmail.com>
Reported-by: NJuha Kuikka <juha.kuikka@gmail.com>
Acked-by: NRajashekhara, Sudhakar <sudhakar.raj@ti.com>
Cc: linux-mmc@vger.kernel.org
Cc: davinci-linux-open-source@linux.davincidsp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: Rajashekhara, Sudhakar <sudhakar.raj@ti.com>
Cc: Ido Yariv <ido@wizery.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

 Use kzalloc rather than kmalloc followed by memset with 0

 This considers some simple cases that are common and easy to validate
 Note in particular that there are no ...s in the rule, so all of the
 matched code has to be contiguous

 The semantic patch that makes this output is available
 in scripts/coccinelle/api/alloc/kzalloc-simple.cocci.

 More information about semantic patching is available at
 http://coccinelle.lip6.fr/Signed-off-by: NThomas Meyer <thomas@m3y3r.de>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Davinci platforms may define a default queue for each channel
controller. If one is not defined, the default queue is set to EVENTQ_1.
However, there's no way to distinguish between an unset default queue to
one that is set to EVENTQ_0, as EVENTQ_0 = 0.

Explicitly specify the default queue for all channel controllers on all
Davinci platforms to EVENTQ_1, and don't overwrite it in the EDMA probe
function.

One exception is the DA850 board, for which EVENTQ_1 is not a valid
option for its second channel controller. Use EVENTQ_0 instead for that
channel controller.
Signed-off-by: NIdo Yariv <ido@wizery.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

If irq2ctlr() fails return IRQ_NONE.
Also as it can fail make 'ctlr' signed.

The semantic patch that finds this problem (many false-positive results):
(http://coccinelle.lip6.fr/)

// <smpl>
@ r1 @
identifier f;
@@
int f(...) { ... }

@@
identifier r1.f;
type T;
unsigned T x;
@@

*x = f(...)
 ...
*x > 0
Signed-off-by: NKulikov Vasiliy <segooon@gmail.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

Current EDMA driver is not taking care of EDMA channels/slots
which are allocated from other processor, say DSP. If a
channel/slot is allocated from DSP, the existing EDMA driver
can still allocate the same resource on ARM.

This patch enables the user to pass the channel/slots reserved
for DSP as platform data. EDMA driver scans this list during
probe and prepares a bitmap of channel/slots which can be used
on ARM side.

Trying to reserve channels by doing a 'pre-allocate' using
edma_alloc_{slot|channel}() API does not work because

1) The reservation should be done in probe() to avoid race
   with other ARM side driver trying to use EDMA

2) The alloc channel API sets up the access through shadow region
   0 which will be incorrect for DSP usage. It also sets up the
   channel <-> queue number mapping which is not required as DSP
   will likely do its own mapping anyway.

3) (minor) There is no API to allocate channels in bulk.
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch modifies the EDMA driver to expect the channel
controller (CC) infomation passed on by the platform as a fixed
size (EDMA_MAX_CC) array of pointers to structures.

Doing so helps catch errors of the sort where the resource
structure has information for more channel controllers than
the number channel controller info structures defined.

Such insufficient platform data would lead to illegal memory
accesses.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

In the edma driver, most of the long lines in 'if condition' are
broken after the logical operator '&&' except two instances.

This patch fixes that to bring consistency across the file.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>

This patch replaces occurences of (1 << x) with
BIT(x) as it makes for much better reading.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>