Nothing uses it, and I can't find any evidence that anything ever has.
Its role is now filled by the core clock in the firmware driver.
Signed-off-by: NEric Anholt <eric@anholt.net>
Acked-by: NStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

While children of orphan clocks are not carried in the orphan-list itself,
they're nevertheless orphans in their own right as they also don't have an
input-rate available. To ease tracking if a clock is an orphan or has an
orphan in its parent path introduce an orphan field into struct clk and
update it and the fields in child-clocks when a clock gets added or removed
from the orphan-list.
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Alex Elder <elder@linaro.org>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Cc: kernel@pengutronix.de
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Cc: Chao Xie <chao.xie@marvell.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Andrew Bresticker <abrestic@chromium.org>
Cc: Robert Jarzmik <robert.jarzmik@free.fr>
Cc: Georgi Djakov <georgi.djakov@linaro.org>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Barry Song <baohua@kernel.org>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Viresh Kumar <viresh.linux@gmail.com>
Cc: Gabriel FERNANDEZ <gabriel.fernandez@st.com>
Cc: emilio@elopez.com.ar
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Michal Simek <michal.simek@xilinx.com>
[sboyd@codeaurora.org: s/clk/core/ in new function]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The gates were handled with a common piece of framework that was
registering all gates array, that was not using the CLK_OF_DECLARE logic,
and was not using clock-indices but some private masks that were pretty
much equivalent.

Move this code in a new driver that handles all the gates array and solves
both these issues.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
[sboyd@codeaurora.org: Include clk.h for consumer API usage]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Wrap the clock-indices to match the wrapping of the clock-output-names in
order to make it easier to match indices to names.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The A23 and A33 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The A20 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The A31 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The A10s and A13 gates have a non continuous set of clock IDs that are
valid. Add the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The A10 gates have a non continuous set of clock IDs that are valid. Add
the clock-indices property to the DT to express this.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Merge tag 'imx-clk-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into clk-next

The i.MX clock updates for 4.3:
 - Provide a better IPU clock initial settings on imx6dl for getting
   HDMI and LVDS at the same time.
 - Add clock driver support for i.MX6UL SoC
 - Add a second clock for RTC device on i.MX31 and i.MX35

The patch was generated using fixed coccinelle semantic patch
scripts/coccinelle/api/memdup.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2014320Signed-off-by: NAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The imx35 don't define clocks for rtc.
This patch add two clocks, as needed
by the mxc rtc driver.
Signed-off-by: NPhilippe Reynes <tremyfr@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

The mxc rtc driver needs two clock.
It was defined only one clock, so we
define the second clock.
Signed-off-by: NPhilippe Reynes <tremyfr@gmail.com>
Signed-off-by: NShawn Guo <shawnguo@kernel.org>

*of_iomap()* will check the device node pointer, and if the pointer is
NULL it will return error code. So refine clock's init flow by checking
the device node with this simple way; and polish a little for the print
out message.
Signed-off-by: NLeo Yan <leo.yan@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The ">" should be ">=" or we end up reading beyond the end of the array.

Fixes: 6e973d2c ('clk: vexpress: Add separate SP810 driver')
Signed-off-by: NDan Carpenter <dan.carpenter@oracle.com>
Acked-by: NPawel Moll <pawel.moll@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The TSADC gate clock was used in Exynos4x12 DTSI for exynos-adc driver.
However TSADC is present only on Exynos4210 so on Trats2 board (with
Exynos4412 SoC) the exynos-adc driver could not be probed:
   ERROR: could not get clock /adc@126C0000:adc(0)
   exynos-adc 126c0000.adc: failed getting clock, err = -2
   exynos-adc: probe of 126c0000.adc failed with error -2

Instead on Exynos4x12 SoCs the main clock used by Analog to Digital
Converter is located in different register and it is named in datasheet
as PCLK_ADC. Regardless of the name the purpose of this PCLK_ADC clock
is the same as purpose of TSADC from Exynos4210.

The patch adds gate clock for Exynos4x12 using the proper register so
backward compatibility is preserved. This fixes the probe of exynos-adc
driver on Exynos4x12 boards and allows accessing sensors connected to it
on Trats2 board (ntc,ncp15wb473 AP and battery thermistors).
Signed-off-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: <stable@vger.kernel.org>
Fixes: c63c5743 ("ARM: dts: Add ADC's dt data to read raw data for exynos4x12")
Reviewed-by: NJavier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

set_irq_flags is ARM specific with custom flags which have genirq
equivalents. Convert drivers to use the genirq interfaces directly, so we
can kill off set_irq_flags. The translation of flags is as follows:

IRQF_VALID -> !IRQ_NOREQUEST
IRQF_PROBE -> !IRQ_NOPROBE
IRQF_NOAUTOEN -> IRQ_NOAUTOEN

For IRQs managed by an irqdomain, the irqdomain core code handles clearing
and setting IRQ_NOREQUEST already, so there is no need to do this in
.map() functions and we can simply remove the set_irq_flags calls. Some
users also modify IRQ_NOPROBE and this has been maintained although it
is not clear that is really needed. There appears to be a great deal of
blind copy and paste of this code.
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: Mike Turquette <mturquette@baylibre.com>
Acked-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The array of parent names can be made as array of const pointers to
const strings.
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add SPDIF/I2S and GPIO clock for zx296702
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Add SPDIF/I2S divider clock method for zx296702
Signed-off-by: NJun Nie <jun.nie@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This patch cleans up the driver for,

  - Use devm_kcalloc() variant instead of devm_kzalloc() for array
    allocation.
  - clk_prepare()/unprepare(), remove "ret" variable as it is not required
  - use __exit for cleanup function

As I am referring this driver as a reference for my 88pm800 clk driver,
applying same changes here as well.
Signed-off-by: NVaibhav Hiremath <vaibhav.hiremath@linaro.org>
Tested-by: NAnand Moon <linux.amoon@gmail.com>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The recursive spinlock implementation trips up sparse and it
complains that these functions have lock imbalances. That isn't
really true though, so add some __acquires() and __releases()
information so that sparse is quiet.

drivers/clk/clk.c:116:22: warning: context imbalance in 'clk_enable_lock' - wrong count at exit
drivers/clk/clk.c:141:9: warning: context imbalance in 'clk_enable_unlock' - unexpected unlock
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The basic clock types use conditional locking for the register
accessor spinlocks. Add __acquire() and __release() markings in
the right locations so that sparse isn't tripped up on the
conditional locking.

drivers/clk/clk-mux.c:68:12: warning: context imbalance in 'clk_mux_set_parent' - different lock contexts for basic block
drivers/clk/clk-divider.c:379:12: warning: context imbalance in 'clk_divider_set_rate' - different lock contexts for basic block
drivers/clk/clk-gate.c:71:9: warning: context imbalance in 'clk_gate_endisable' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:36:9: warning: context imbalance in 'clk_fd_recalc_rate' - different lock contexts for basic block
drivers/clk/clk-fractional-divider.c:68:12: warning: context imbalance in 'clk_fd_set_rate' - different lock contexts for basic block

Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The missing license causes the clk-qcom.ko module to taint the
kernel. Add the appropriate license to avoid taint.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Let's encourage const arrays of parent names like other basic
clock types.

Cc: Sergej Sawazki <ce3a@gmx.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next

This commit allows certain Broadcom STB clock dividers to be used with
clk-divider.c.  It allows for a clock whose field value is the equal
to the divisor, execpt when the field value is zero, in which case the
divisor is 2^width.  For example, consider a divisor clock with a two
bit field:

value		divisor
0		4
1		1
2		2
3		3
Signed-off-by: NJim Quinlan <jim2101024@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Convert the code to use GENMASK() helper instead of div_mask() macro.
Signed-off-by: NAndy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Legacy drivers which are not yet ported, such as cpufreq-pxa[23]xx, rely
on pxaXXx_get_clk_frequency_khz() to find the CPU core frequency.

This reporting was broken because the expected unit is kHz and not
Hz. Fix the reporting for pxa25x, pxa27x and pxa3xx.

Fixes: fe7710fa ("clk: add pxa25x clock drivers")
Fixes: d40670dc ("clk: add pxa27x clock drivers")
Fixes: 9bbb8a33 ("clk: pxa: add pxa3xx clock driver")
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

In the TRM we see that BWADJ is "a 12-bit bus that selects the values
1-4096 for the bandwidth divider (NB)":
 NB = BWADJ[11:0] + 1
The recommended setting of NB: NB = NF / 2.

So:
  NB = NF / 2
  BWADJ[11:0] + 1 = NF / 2
  BWADJ[11:0] = NF / 2 - 1

Right now, we have:

{                                               \
        .rate   = _rate##U,                     \
        .nr = _nr,                              \
        .nf = _nf,                              \
        .no = _no,                              \
        .bwadj = (_nf >> 1),                    \
}

That means we set bwadj to NF / 2, not NF / 2 - 1

All of this is a bit confusing because we specify "NR" (the 1-based
value), "NF" (the 1-based value), "NO" (the 1-based value), but
"BWADJ" (the 0-based value) instead of "NB" (the 1-based value).

Let's change to working with "NB" and fix the off by one error.  This
may affect PLL jitter in a small way (hopefully for the better).
Signed-off-by: NDouglas Anderson <dianders@chromium.org>
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

* cleanup-clk-h-includes: (62 commits)
  clk: Remove clk.h from clk-provider.h
  clk: h8300: Remove clk.h and clkdev.h includes
  clk: at91: Include clk.h and slab.h
  clk: ti: Switch clk-provider.h include to clk.h
  clk: pistachio: Include clk.h
  clk: ingenic: Include clk.h
  clk: si570: Include clk.h
  clk: moxart: Include clk.h
  clk: cdce925: Include clk.h
  clk: Include clk.h in clk.c
  clk: zynq: Include clk.h
  clk: ti: Include clk.h
  clk: sunxi: Include clk.h and remove unused clkdev.h includes
  clk: st: Include clk.h
  clk: qcom: Include clk.h
  clk: highbank: Include clk.h
  clk: bcm: Include clk.h
  clk: versatile: Remove clk.h and clkdev.h includes
  clk: ux500: Remove clk.h and clkdev.h includes
  clk: tegra: Properly include clk.h
  ...

Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Tested-by Gabriel Fernandez <gabriel.fernandez@st.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: NSantosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use of_clk_parent_fill to fill in the parent clock names' array.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.

This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
Signed-off-by: NJames Liao <jamesjj.liao@mediatek.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

clk providers are using the consumer APIs to set min/max rates on
the clock they're providing. To encourage clk providers to move
away from the consumer APIs, add a provider API to set the
min/max rate of a clock. The assumption is that this is done
before the clock can be requested via clk_get() and that the
clock rate is already within the boundaries of the min/max that's
configured.
Tested-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>