1. 24 8月, 2016 4 次提交
  2. 11 8月, 2016 7 次提交
  3. 09 8月, 2016 6 次提交
  4. 08 8月, 2016 5 次提交
  5. 05 8月, 2016 2 次提交
  6. 04 8月, 2016 1 次提交
  7. 25 7月, 2016 2 次提交
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  10. 18 7月, 2016 1 次提交
    • C
      ASoC: rockchip: correct the spdif clk · 46dd2e28
      Chris Zhong 提交于
      The spdif mclk should be 128 times of sample rate, and there is a
      internal divider, the real rate of spdif mclk is mclk / (div + 1).
      Hence, the original driver always get the good frequency for
      48000/96000/44100/192000. But for 32000, the mclk is incorrect,
      it should be 32000*128, but get 48000*128. Do not use the internal
      divider here, just set all mclk to 128 * sample rate directly.
      Signed-off-by: NChris Zhong <zyw@rock-chips.com>
      Signed-off-by: NMark Brown <broonie@kernel.org>
      46dd2e28
  11. 16 7月, 2016 7 次提交
  12. 15 7月, 2016 1 次提交