1. 06 6月, 2014 4 次提交
    • T
      drm/tegra: hdmi - Clean up clock usage · d06e7f8f
      Thierry Reding 提交于
      Clocks are never enabled or disabled in atomic context, so we can use
      the clk_prepare_enable() and clk_disable_unprepare() helpers instead.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      d06e7f8f
    • T
      drm/tegra: hdmi - Reverse regulator enable ordering · 88685687
      Thierry Reding 提交于
      Schematics indicate that the AVDD_HDMI_PLL supply should be enabled
      prior to the AVDD_HDMI supply.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      88685687
    • T
      drm/tegra: hdmi - Remove duplicate code · 80b92139
      Thierry Reding 提交于
      The generic Tegra output code already sets up the clocks properly, so
      there's no need to do it again when the HDMI output is enabled.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      80b92139
    • T
      drm/tegra: hdmi - Add connector supply support · fb50a116
      Thierry Reding 提交于
      Revert commit 18ebc0f4 "drm/tegra: hdmi: Enable VDD earlier for
      hotplug/DDC" and instead add a new supply for the +5V pin on the HDMI
      connector.
      
      The vdd-supply property refers to the regulator that supplies the
      AVDD_HDMI input on Tegra, rather than the +5V HDMI connector pin. This
      was never a problem before, because all boards had that pin hooked up to
      a regulator that was always on. Starting with Dalmore and continuing
      with Venice2, the +5V pin is controllable via a GPIO. For reasons
      unknown, the GPIO ended up as the controlling GPIO of the AVDD_HDMI
      supply in the Dalmore and Venice2 DTS files. But that's not correct.
      Instead, a separate supply must be introduced so that the +5V pin can be
      controlled separately from the supplies that feed the HDMI block within
      Tegra.
      
      A new hdmi-supply property is introduced that takes the place of the
      vdd-supply and vdd-supply is only enabled when HDMI is enabled rather
      than all the time.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      fb50a116
  2. 14 1月, 2014 1 次提交
  3. 20 12月, 2013 1 次提交
  4. 19 12月, 2013 3 次提交
    • T
      drm/tegra: Track HDMI enable state · 365765fc
      Thierry Reding 提交于
      The DRM core doesn't track enable and disable state of encoders and/or
      connectors, so calls to the output's .enable() and .disable() are not
      guaranteed to be balanced. Track the enable state internally so that
      calls to regulator and clock frameworks remain balanced.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      365765fc
    • T
      drm/tegra: Fix HDMI audio frequency typo · 17a8b6b0
      Thierry Reding 提交于
      The correct check is for 48 kHz, not 480 kHz. Found by Coverity.
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      17a8b6b0
    • P
      gpu: host1x: clk_round_rate() can return a zero upon error · 23a0e27a
      Paul Walmsley 提交于
      Treat both negative and zero return values from clk_round_rate() as
      errors.  This is needed since subsequent patches will convert
      clk_round_rate()'s return value to be an unsigned type, rather than a
      signed type, since some clock sources can generate rates higher than
      (2^31)-1 Hz.
      
      Eventually, when calling clk_round_rate(), only a return value of zero
      will be considered a error.  All other values will be considered valid
      rates.  The comparison against values less than 0 is kept to preserve
      the correct behavior in the meantime.
      Signed-off-by: NPaul Walmsley <pwalmsley@nvidia.com>
      Cc: Mikko Perttunen <mperttunen@nvidia.com>
      Cc: Arto Merilainen <amerilainen@nvidia.com>
      Cc: Thierry Reding <thierry.reding@gmail.com>
      Cc: Terje Bergström <tbergstrom@nvidia.com>
      Signed-off-by: NThierry Reding <treding@nvidia.com>
      23a0e27a
  5. 12 12月, 2013 1 次提交
  6. 31 10月, 2013 13 次提交
  7. 30 8月, 2013 2 次提交
  8. 27 8月, 2013 1 次提交
  9. 22 4月, 2013 3 次提交
  10. 22 2月, 2013 1 次提交
  11. 29 1月, 2013 1 次提交
  12. 26 1月, 2013 1 次提交
  13. 30 12月, 2012 2 次提交
  14. 28 11月, 2012 1 次提交
  15. 20 11月, 2012 1 次提交