This commit introduces the clocks found in the Allwinner A33 CCU.

Since this SoC is very similar to the A23, and we share a significant share
of the DTSI, the clock IDs that are going to be used will also be shared
with the A23, hence the name of the various header files.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

Add support for the class with a single factor, N, being a multiplier.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

Add a new macro to declare muxes based on a table and a gate.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

Some dividers might have a maximum value that is lower than the width of
the register.

Add a field to _ccu_div to handle those case properly. If the field is set
to 0, the code will assume that the maximum value is the maximum one that
can be used with the field register width.

Otherwise, we'll use whatever value has been set.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

The internal _ccu_div structure is meant to be embedded into other
structures to combine the various dividers and to form the clock classes
support.

Start to document those structures by using kerneldoc.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Add some macros to ease the declaration of clocks that are using them.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NChen-Yu Tsai <wens@csie.org>

Add a new style driver for the clock control unit in Allwinner A31/A31s.

A few clocks are still missing:

    - MIPI PLL's HDMI mode support
    - EMAC clock
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Acked-by: NRob Herring <robh@kernel.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

On sunxi we support cpufreq by changing the clock rate of PLL-CPU.
It's possible the clock output of the PLL goes out of the CPU's
operational limits when the PLL's multipliers / dividers are changed
and it hasn't stabilized yet. This would result in the CPU hanging.

To circumvent this, we temporarily switch the CPU mux clock to another
stable clock before the rate change, and switch it back after the PLL
stabilizes. This is done with clk notifiers registered on the PLL.

This patch adds common functions for notifiers to reparent mux clocks.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some clocks on the A31 have fixed pre-dividers on multiple parents.
Add support for them.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some clock muxes have holes, i.e. invalid or unconnected inputs,
between parent mux values.

Add support for specifying a mux table to map clock parents to
mux values.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Rename the internal mux macro to be consistent with the other internal
structure macros.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The MIPI mode of the MIPI-PLL on A31 is an NKM-style PLL with 2
selectable parents.

Add mux support to the NKM clock.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Some clocks have a predivider value that is larger than what u8 can
store. One such example is the OUT clk found on A20/A31, which has
a /750 pre-divider on one of the osc24M parents.

Increase the size of the div field to u16.
Signed-off-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

The Kconfig symbol for the sun8i SoC family was mistyped. Fix that.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160711203448.18062-2-maxime.ripard@free-electrons.com

The code had a typo and got the wrong offset for the hardcoded divider, fix
that.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Reported-by: NJean-Francois Moine <moinejf@free.fr>
Reported-by: NChen-Yu Tsai <wens@csie.org>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com

Add the list of clocks and resets found in the H3 CCU.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-14-maxime.ripard@free-electrons.com

Introduce support for clocks that use a combination of two linear
multipliers (N and K factors), one linear divider (M) and one power of two
divider (P).
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-13-maxime.ripard@free-electrons.com

Introduce support for clocks that multiply and divide using two linear
multipliers and one linear divider.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-12-maxime.ripard@free-electrons.com

Introduce support for clocks that multiply and divide using linear factors.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-11-maxime.ripard@free-electrons.com

Introduce support for clocks that use a combination of two linear
multipliers.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-10-maxime.ripard@free-electrons.com

Introduce support for the clocks that combine a linear divider and a
power-of-two based one.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-9-maxime.ripard@free-electrons.com

Add support for the various dividers (linear, table or pow-of-two based)
found in the CCU.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-8-maxime.ripard@free-electrons.com

Add support for the clocks in the CCU that introduce a phase shift from
their parent clock.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-7-maxime.ripard@free-electrons.com

Some clocks in the Allwinner SoCs clocks unit are just muxes.

However, those muxes might also be found in some other complicated clocks
that would benefit from the code in there to deal with "advanced" features,
like pre-dividers.

Introduce a set of helpers to reduce the code duplication in such cases.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-6-maxime.ripard@free-electrons.com

Some clocks in the Allwinner SoCs clocks unit are just simple gates. Add
support for those clocks.

Since it's a feature that can also be found in more complex clocks, provide
a bunch of helpers that can be reused later on.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-5-maxime.ripard@free-electrons.com

Some clocks can be switched to a mode called fractional that have two fixed
output rate you can choose from.

Add a small library to deal with those clocks.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-4-maxime.ripard@free-electrons.com

Start our new clock infrastructure by adding the registration code, common
structure and common code.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20160629190535.11855-3-maxime.ripard@free-electrons.com