arg is long int, so arg = (arg << 22) >> 22 makes the upper 22 bits of
arg equal to bit 9 (or bit 41). But we then mask away all but bits 0-9, so
this is entirely redundant.
Signed-off-by: NRasmus Villemoes <linux@rasmusvillemoes.dk>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

This change is needed to properly lock I2C bus device and driver,
which serve DDC lines. Without this change I2C bus driver module
may gone in runtime and this won't be noticed by the driver.
Signed-off-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

The commit 53bdcf5f ("drm: sti: fix sub-components bind") moves
i2c adapter search and locking from .bind() to .probe(), however
proper error path in the modified .probe() is not implemented and
leftover of the related error path in .bind() remains. This change
fixes these issues.

Fixes: 53bdcf5f ("drm: sti: fix sub-components bind")
Signed-off-by: NVladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

None of these exported symbols are used outside of the drm-sti driver,
so there is no reason to export them.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

There's no use building the individual drivers as separate modules
because they are all only useful if combined into a single DRM/KMS
device.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

Non-legacy drivers should only use this API to allow per-CRTC data to be
eventually moved into struct drm_crtc.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

A negative pipe causes a special case to be triggered for drivers that
don't have proper VBLANK support. STi does support VBLANKs, so there is
no need for the fallback code.

Cc: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Cc: Vincent Abriou <vincent.abriou@st.com>
Signed-off-by: NThierry Reding <treding@nvidia.com>
Reviewed-by: NVincent Abriou <vincent.abriou@st.com>

Select FW_LOADER explicitly to satify the direct dependency of
FW_LOADER_USER_HELPER_FALLBACK.
Acked-by: NBenjamin Gaignard <benjamin.gaignard@linaro.org>
Signed-off-by: NThierry Reding <treding@nvidia.com>

Moves a bunch of junk to .rodata from .data.

 drivers/gpu/drm/sti/sticompositor.ko:
-.text                       12216
+.text                       12212
-.rodata                      1284
+.rodata                      1400
-.data                         488
+.data                         372

 drivers/gpu/drm/sti/sti_drv.ko:
-.rodata                      516
+.rodata                      544
-.data                        368
+.data                        340

 drivers/gpu/drm/sti/stidvo.ko:
-.text                       3356
+.text                       3348
-.rodata                      188
+.rodata                      256
-.data                        572
+.data                        504

 drivers/gpu/drm/sti/sti_hda.ko:
-.text                       3008
+.text                       3004
-.rodata                     2820
+.rodata                     2888
-.data                        684
+.data                        616

 drivers/gpu/drm/sti/stihdmi.ko:
-.text                        6988
+.text                        6980
-.rodata                      1340
+.rodata                      1408
-.data                         176
+.data                         108
Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: NAlex Deucher <alexander.deucher@amd.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

USIF already takes the client mutex, but will need access to ABI16 data
in order to provide some limited interoperability.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91557Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70354#c75Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

This patch uses an approach closer to the nvidia driver to configure
both PLLs for high gddr5 memory clocks (usually above 2400MHz)

Previously nouveau used the one PLL as it was used for the lower clocks
and just adjusted the second PLL to get as close as possible to the
requested clock.  This means for my card, that I got a 4050 MHz clock
although 4008 MHz was requested.

Now the driver iterates over a list of PLL configuration also used by
the nvidia driver and then adjust the second PLL to get near the
requested clock.  Also it hold to some restriction I found while
analyzing the PLL configurations

This won't fix all gddr5 high clock issues itself, but it should be
fine on hybrid gpu systems as found on many laptops these days.  Also
switching while normal desktop usage should be a lot more stable than
before.

v2: move the pll code into ramgk104
Signed-off-by: NKarol Herbst <nouveau@karolherbst.de>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Your milage may vary, as it's only been tested on a single G94 and one G96.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Avoids waiting for VBLANKS that never arrive on headless or otherwise
unconventional set-ups. Strategy taken from MEMX.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

10053c is not even read on some cards, and I have no idea exactly what the
criteria are. Likely NVIDIA pre-scans the VBIOS and in their driver disables
all features that are never used. The practical effect should be the same
as this implementation though.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Like Pierre's G94. We might want to structure Kepler similarly in a follow-up.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Does not seem to be necessary for NVA0, hence untested by me.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Tested-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Seems to be mostly equal to DDR3 on < GT218, should improve stability for
DDR2 reclocks.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

In preparation of changing FBVDDQ, as observed on at least one GDDR3 card.
While at it, adhere to func.log[1] properly for consistency.
Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NRoy Spliet <rspliet@eclipso.eu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

If the hardware supports extended tag field (8-bit ones), then enable it.

This is usually done by the VBIOS, but not on some MBPs (see fdo#86537).

In case extended tag field is not supported, 5-bit tag field is used which
limits the possible number of requests to 32. Apparently bits 7:0 of
0x08841c stores some number of outstanding requests, so cap it to 32 if
extended tag is unsupported.

Fixes: fdo#86537

v2: Restrict changes to chipsets >= 0x84
v3:
  * Add nvkm_pci_mask to pci.h
  * Mask bit 8 before setting it
v4:
  * Rename `add` argument of nvkm_pci_mask to `value`
  * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset
    checks
v5:
  * Rebase code on latest PCI structure
  * Restore PCIe check
  * Fix namings in nvkm_pci_mask
  * Rephrase part of the commit message
Signed-off-by: NPierre Moreau <pierre.morrow@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

These nvkm_object_func structures are never modified.  All other
nvkm_object_func structures are declared as const.

Done with the help of Coccinelle.
Signed-off-by: NJulia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

GF110+ supports both the A and B compute classes, make sure to accept
both.
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

NVIDIA provided the documentation for mp error 0x10, INVALID_ADDR_SPACE,
which apparently happens when trying to use an atomic operation on
local or shared memory (instead of global memory).
Signed-off-by: NIlia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

If pm_runtime_get_sync() we were going to "out" but we missed freeing
vma.
Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

coverity.com reported that memset was using a buffer of size 0, on
checking the code it turned out that the function was not being used. So
remove it.
Signed-off-by: NSudip Mukherjee <sudip@vectorindia.org>
Reviewed-by: NSamuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Reported to be needed as per fdo#70354 comment #61.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Not 100% confirmed, but seems to match from the few boards I've looked
at so far.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Was not able to obtain a trace of NVRM due to kernel version annoyances,
however, experimentally confirmed that the WAR we use on NV50/G8x boards
works here too.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

An upcoming patch will implement functionality that we don't use on any
NV40 chipset.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

An upcoming patch will implement functionality that we don't use on the
original NV50.
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Increase clock timeout of some unknown engines in order to avoid failure
at high gpcclk rate.

This fixes IBUS read faults on my GF119 when reclocking is manually
enabled. Note that memory reclocking is completely broken and NvMemExec
has to be disabled to allow core clock reclocking only.
Signed-off-by: NSamuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

I got confirmation that we can read and change the voltage with the same code.
The divider is also computed correctly on the gm204 we got our hands on.

Thanks to Yoshimo on IRC for executing the tests on his gm204!
Signed-off-by: NMartin Peres <martin.peres@free.fr>
Signed-off-by: NBen Skeggs <bskeggs@redhat.com>

Let's ignore the other desktop Maxwells until I get my hands on one and confirm
that we still can change the voltage.
Signed-off-by: NMartin Peres <martin.peres@free.fr>