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  1. 10 3月, 2019 2 次提交
  3. 23 2月, 2019 1 次提交
    • J
      dsa: mv88e6xxx: Ensure all pending interrupts are handled prior to exit · 017d5110
      由 John David Anglin 提交于 
      [ Upstream commit 7c0db24cc431e2196d98a5d5ddaa9088e2fcbfe5 ]

The GPIO interrupt controller on the espressobin board only supports edge interrupts.
If one enables the use of hardware interrupts in the device tree for the 88E6341, it is
possible to miss an edge.  When this happens, the INTn pin on the Marvell switch is
stuck low and no further interrupts occur.

I found after adding debug statements to mv88e6xxx_g1_irq_thread_work() that there is
a race in handling device interrupts (e.g. PHY link interrupts).  Some interrupts are
directly cleared by reading the Global 1 status register.  However, the device interrupt
flag, for example, is not cleared until all the unmasked SERDES and PHY ports are serviced.
This is done by reading the relevant SERDES and PHY status register.

The code only services interrupts whose status bit is set at the time of reading its status
register.  If an interrupt event occurs after its status is read and before all interrupts
are serviced, then this event will not be serviced and the INTn output pin will remain low.

This is not a problem with polling or level interrupts since the handler will be called
again to process the event.  However, it's a big problem when using level interrupts.

The fix presented here is to add a loop around the code servicing switch interrupts.  If
any pending interrupts remain after the current set has been handled, we loop and process
the new set.  If there are no pending interrupts after servicing, we are sure that INTn has
gone high and we will get an edge when a new event occurs.

Tested on espressobin board.

Fixes: dc30c35b ("net: dsa: mv88e6xxx: Implement interrupt support.")
Signed-off-by: NJohn David Anglin <dave.anglin@bell.net>
Tested-by: NAndrew Lunn <andrew@lunn.ch>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
Signed-off-by: NSasha Levin <sashal@kernel.org>
      017d5110
  5. 13 2月, 2019 1 次提交
  7. 26 1月, 2019 1 次提交
  9. 23 1月, 2019 1 次提交
  11. 21 12月, 2018 1 次提交
  13. 23 11月, 2018 2 次提交
  15. 14 11月, 2018 1 次提交
  17. 12 10月, 2018 2 次提交
    • F
      net: dsa: bcm_sf2: Call setup during switch resume · 54baca09
      由 Florian Fainelli 提交于 
      There is no reason to open code what the switch setup function does, in
fact, because we just issued a switch reset, we would make all the
register get their default values, including for instance, having unused
port be enabled again and wasting power and leading to an inappropriate
switch core clock being selected.

Fixes: 8cfa9498 ("net: dsa: bcm_sf2: add suspend/resume callbacks")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      54baca09
    • F
      net: dsa: bcm_sf2: Fix unbind ordering · bf3b452b
      由 Florian Fainelli 提交于 
      The order in which we release resources is unfortunately leading to bus
errors while dismantling the port. This is because we set
priv->wol_ports_mask to 0 to tell bcm_sf2_sw_suspend() that it is now
permissible to clock gate the switch. Later on, when dsa_slave_destroy()
comes in from dsa_unregister_switch() and calls
dsa_switch_ops::port_disable, we perform the same dismantling again, and
this time we hit registers that are clock gated.

Make sure that dsa_unregister_switch() is the first thing that happens,
which takes care of releasing all user visible resources, then proceed
with clock gating hardware. We still need to set priv->wol_ports_mask to
0 to make sure that an enabled port properly gets disabled in case it
was previously used as part of Wake-on-LAN.

Fixes: d9338023 ("net: dsa: bcm_sf2: Make it a real platform device driver")
Signed-off-by: NFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      bf3b452b
  19. 05 10月, 2018 1 次提交
  21. 17 9月, 2018 1 次提交
  23. 17 8月, 2018 1 次提交
  25. 15 8月, 2018 2 次提交
  27. 10 8月, 2018 13 次提交
  29. 08 8月, 2018 2 次提交
  31. 04 8月, 2018 2 次提交
  33. 01 8月, 2018 1 次提交
  35. 23 7月, 2018 1 次提交
  37. 22 7月, 2018 1 次提交
    • U
      net: dsa: mv88e6xxx: fix races between lock and irq freeing · 3d82475a
      由 Uwe Kleine-König 提交于 
      free_irq() waits until all handlers for this IRQ have completed. As the
relevant handler (mv88e6xxx_g1_irq_thread_fn()) takes the chip's reg_lock
it might never return if the thread calling free_irq() holds this lock.

For the same reason kthread_cancel_delayed_work_sync() in the polling case
must not hold this lock.

Also first free the irq (or stop the worker respectively) such that
mv88e6xxx_g1_irq_thread_work() isn't called any more before the irq
mappings are dropped in mv88e6xxx_g1_irq_free_common() to prevent the
worker thread to call handle_nested_irq(0) which results in a NULL-pointer
exception.
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      3d82475a
  39. 19 7月, 2018 3 次提交