1. 10 6月, 2014 1 次提交
  2. 02 6月, 2014 4 次提交
  3. 30 5月, 2014 1 次提交
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  5. 04 3月, 2014 1 次提交
  6. 03 3月, 2014 4 次提交
  7. 30 1月, 2014 2 次提交
  8. 03 12月, 2013 2 次提交
  9. 16 11月, 2013 2 次提交
  10. 02 11月, 2013 3 次提交
  11. 08 8月, 2013 1 次提交
  12. 23 7月, 2013 1 次提交
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  14. 14 7月, 2013 1 次提交
  15. 12 6月, 2013 1 次提交
  16. 02 2月, 2013 1 次提交
  17. 10 12月, 2012 1 次提交
  18. 07 11月, 2012 1 次提交
  19. 24 10月, 2012 1 次提交
  20. 23 10月, 2012 3 次提交
  21. 16 10月, 2012 3 次提交
  22. 03 10月, 2012 1 次提交
  23. 27 9月, 2012 2 次提交
    • D
      drm/radeon: add 2-level VM pagetables support v9 · fa87e62d
      Dmitry Cherkasov 提交于
      PDE/PTE update code uses CP ring for memory writes.
      All page table entries are preallocated for now in alloc_pt().
      
      It is made as whole because it's hard to divide it to several patches
      that compile and doesn't break anything being applied separately.
      
      Tested on cayman card.
      
      v2: rebased on top of "refactor set_page chipset interface v3",
          code cleanups
      
      v3: switched offsets calc macros to inline funcs where possible,
          remove pd_addr from radeon_vm, switched RADEON_BLOCK_SIZE define,
          to 9 (and PTE_COUNT to 1 << BLOCK_SIZE)
      
      v4 (ck): move "incr" documentation to previous patch, cleanup and
               document RADEON_VM_* constants, change commit message to
               our usual format, simplify patch allot by removing
               everything current not necessary, disable SI workaround.
      
      v5: (agd5f): Fix typo in tables_size calculation in
                   radeon_vm_alloc_pt().  Second line should have been
                   '+=' rather than '='.
      
      v6: fix npdes calculation. In scenario when pfns to be mapped overlap
      two PDE spans:
      
         +-----------+-------------+
         | PDE span  | PDE span    |
         +-----------+----+--------+
                |         |
                +---------+
                | pfns    |
                +---------+
      
      the following npdes calculation gives incorrect result:
      
      npdes = (nptes >> RADEON_VM_BLOCK_SIZE) + 1;
      
      For the case above picture it should give npdes = 2, but gives one.
      
      This patch corrects it by rounding last pfn up to 512 border,
      first - down to 512 border and then subtracting and dividing by 512.
      
      v7: Make npde calculation clearer, fix ndw calculation.
      
      v8: (agd5f): reserve enough for 2 full VM PTs, add some
                   additional comments.
      
      v9: fix typo in npde calculation
      Signed-off-by: NDmitry Cherkasov <Dmitrii.Cherkasov@amd.com>
      Signed-off-by: NChristian König <deathsimple@vodafone.de>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      fa87e62d
    • C
      drm/radeon: refactor set_page chipset interface v5 · dce34bfd
      Christian König 提交于
      Cleanup the interface in preparation for hierarchical page tables.
      
      v2: add incr parameter to set_page for simple scattered PTs uptates
          added PDE-specific flags to r600_flags and radeon_drm.h
          removed superfluous value masking with 0xffffffff
      
      v3: removed superfluous bo_va->valid checking
          changed R600_PTE_VALID to R600_ENTRY_VALID to handle PDE too
      
      v4 (ck): fix indention style, rework and fix typos in commit message,
               add documentation for incr parameter, also use incr
               parameter for system pages
      
      v5 (agd5f): use upper_32_bits() and minor white space fixes
      Signed-off-by: NChristian König <deathsimple@vodafone.de>
      Signed-off-by: NDmitry Cherkassov <Dmitrii.Cherkasov@amd.com>
      Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
      dce34bfd
  24. 21 9月, 2012 1 次提交