1. 30 4月, 2013 1 次提交
  2. 16 1月, 2013 1 次提交
  3. 10 1月, 2013 2 次提交
    • M
      powerpc: Hardware breakpoints rewrite to handle non DABR breakpoint registers · 9422de3e
      Michael Neuling 提交于
      This is a rewrite so that we don't assume we are using the DABR throughout the
      code.  We now use the arch_hw_breakpoint to store the breakpoint in a generic
      manner in the thread_struct, rather than storing the raw DABR value.
      
      The ptrace GET/SET_DEBUGREG interface currently passes the raw DABR in from
      userspace.  We keep this functionality, so that future changes (like the POWER8
      DAWR), will still fake the DABR to userspace.
      Signed-off-by: NMichael Neuling <mikey@neuling.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      9422de3e
    • A
      powerpc: Build kernel with -mcmodel=medium · 1fbe9cf2
      Anton Blanchard 提交于
      Finally remove the two level TOC and build with -mcmodel=medium.
      
      Unfortunately we can't build modules with -mcmodel=medium due to
      the tricks the kernel module loader plays with percpu data:
      
      # -mcmodel=medium breaks modules because it uses 32bit offsets from
      # the TOC pointer to create pointers where possible. Pointers into the
      # percpu data area are created by this method.
      #
      # The kernel module loader relocates the percpu data section from the
      # original location (starting with 0xd...) to somewhere in the base
      # kernel percpu data space (starting with 0xc...). We need a full
      # 64bit relocation for this to work, hence -mcmodel=large.
      
      On older kernels we fall back to the two level TOC (-mminimal-toc)
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      1fbe9cf2
  4. 15 11月, 2012 9 次提交
  5. 18 9月, 2012 1 次提交
    • M
      powerpc: Add an xmon command to dump one or all pacas · ddadb6b8
      Michael Ellerman 提交于
      This was originally motivated by a desire to see the mapping between
      logical and hardware cpu numbers.
      
      But it seemed that it made more sense to just add a command to dump
      (most of) the paca.
      
      With no arguments "dp" will dump the paca for the current cpu.
      
      It also takes an argument, eg. "dp 3" which is the logical cpu number
      in hex. This form does not check if the cpu is possible, but displays
      the paca regardless, as well as the cpu's state in the possible, present
      and online masks.
      
      Thirdly, "dpa" will display the paca for all possible cpus. If there are
      no possible cpus, like early in boot, it will tell you that.
      
      Sample output, number in brackets is the offset into the struct:
      
      2:mon> dp 3
      paca for cpu 0x3 @ c00000000ff20a80:
       possible         = yes
       present          = yes
       online           = yes
       lock_token       = 0x8000            	(0x8)
       paca_index       = 0x3               	(0xa)
       kernel_toc       = 0xc00000000144f990	(0x10)
       kernelbase       = 0xc000000000000000	(0x18)
       kernel_msr       = 0xb000000000001032	(0x20)
       stab_real        = 0x0               	(0x28)
       stab_addr        = 0x0               	(0x30)
       emergency_sp     = 0xc00000003ffe4000	(0x38)
       data_offset      = 0xa40000          	(0x40)
       hw_cpu_id        = 0x9               	(0x50)
       cpu_start        = 0x1               	(0x52)
       kexec_state      = 0x0               	(0x53)
       __current        = 0xc00000007e568680	(0x218)
       kstack           = 0xc00000007e5a3e30	(0x220)
       stab_rr          = 0x1a              	(0x228)
       saved_r1         = 0xc00000007e7cb450	(0x230)
       trap_save        = 0x0               	(0x240)
       soft_enabled     = 0x0               	(0x242)
       irq_happened     = 0x0               	(0x243)
       io_sync          = 0x0               	(0x244)
       irq_work_pending = 0x0               	(0x245)
       nap_state_lost   = 0x0               	(0x246)
      Signed-off-by: NMichael Ellerman <michael@ellerman.id.au>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      ddadb6b8
  6. 10 9月, 2012 1 次提交
  7. 24 8月, 2012 2 次提交
  8. 02 7月, 2012 1 次提交
    • A
      powerpc/xmon: Use cpumask iterator to avoid warning · bc1d7702
      Anton Blanchard 提交于
      We have a bug report where the kernel hits a warning in the cpumask
      code:
      
      WARNING: at include/linux/cpumask.h:107
      
      Which is:
              WARN_ON_ONCE(cpu >= nr_cpumask_bits);
      
      The backtrace is:
              cpu_cmd
              cmds
              xmon_core
              xmon
              die
      
      xmon is iterating through 0 to NR_CPUS. I'm not sure why we are still
      open coding this but iterating above nr_cpu_ids is definitely a bug.
      
      This patch iterates through all possible cpus, in case we issue a
      system reset and CPUs in an offline state call in.
      
      Perhaps the old code was trying to handle CPUs that were in the
      partition but were never started (eg kexec into a kernel with an
      nr_cpus= boot option). They are going to die way before we get into
      xmon since we haven't set any kernel state up for them.
      Signed-off-by: NAnton Blanchard <anton@samba.org>
      CC: <stable@kernel.org>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      bc1d7702
  9. 29 3月, 2012 1 次提交
  10. 21 3月, 2012 1 次提交
  11. 09 3月, 2012 2 次提交
    • B
      powerpc: Rework lazy-interrupt handling · 7230c564
      Benjamin Herrenschmidt 提交于
      The current implementation of lazy interrupts handling has some
      issues that this tries to address.
      
      We don't do the various workarounds we need to do when re-enabling
      interrupts in some cases such as when returning from an interrupt
      and thus we may still lose or get delayed decrementer or doorbell
      interrupts.
      
      The current scheme also makes it much harder to handle the external
      "edge" interrupts provided by some BookE processors when using the
      EPR facility (External Proxy) and the Freescale Hypervisor.
      
      Additionally, we tend to keep interrupts hard disabled in a number
      of cases, such as decrementer interrupts, external interrupts, or
      when a masked decrementer interrupt is pending. This is sub-optimal.
      
      This is an attempt at fixing it all in one go by reworking the way
      we do the lazy interrupt disabling from the ground up.
      
      The base idea is to replace the "hard_enabled" field with a
      "irq_happened" field in which we store a bit mask of what interrupt
      occurred while soft-disabled.
      
      When re-enabling, either via arch_local_irq_restore() or when returning
      from an interrupt, we can now decide what to do by testing bits in that
      field.
      
      We then implement replaying of the missed interrupts either by
      re-using the existing exception frame (in exception exit case) or via
      the creation of a new one from an assembly trampoline (in the
      arch_local_irq_enable case).
      
      This removes the need to play with the decrementer to try to create
      fake interrupts, among others.
      
      In addition, this adds a few refinements:
      
       - We no longer  hard disable decrementer interrupts that occur
      while soft-disabled. We now simply bump the decrementer back to max
      (on BookS) or leave it stopped (on BookE) and continue with hard interrupts
      enabled, which means that we'll potentially get better sample quality from
      performance monitor interrupts.
      
       - Timer, decrementer and doorbell interrupts now hard-enable
      shortly after removing the source of the interrupt, which means
      they no longer run entirely hard disabled. Again, this will improve
      perf sample quality.
      
       - On Book3E 64-bit, we now make the performance monitor interrupt
      act as an NMI like Book3S (the necessary C code for that to work
      appear to already be present in the FSL perf code, notably calling
      nmi_enter instead of irq_enter). (This also fixes a bug where BookE
      perfmon interrupts could clobber r14 ... oops)
      
       - We could make "masked" decrementer interrupts act as NMIs when doing
      timer-based perf sampling to improve the sample quality.
      
      Signed-off-by-yet: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      ---
      
      v2:
      
      - Add hard-enable to decrementer, timer and doorbells
      - Fix CR clobber in masked irq handling on BookE
      - Make embedded perf interrupt act as an NMI
      - Add a PACA_HAPPENED_EE_EDGE for use by FSL if they want
        to retrigger an interrupt without preventing hard-enable
      
      v3:
      
       - Fix or vs. ori bug on Book3E
       - Fix enabling of interrupts for some exceptions on Book3E
      
      v4:
      
       - Fix resend of doorbells on return from interrupt on Book3E
      
      v5:
      
       - Rebased on top of my latest series, which involves some significant
      rework of some aspects of the patch.
      
      v6:
       - 32-bit compile fix
       - more compile fixes with various .config combos
       - factor out the asm code to soft-disable interrupts
       - remove the C wrapper around preempt_schedule_irq
      
      v7:
       - Fix a bug with hard irq state tracking on native power7
      7230c564
    • B
      powerpc/xmon: Add display of soft & hard irq states · 7ac21cd4
      Benjamin Herrenschmidt 提交于
      Also use local_paca instead of get_paca() to avoid getting into
      the smp_processor_id() debugging code from the debugger
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      7ac21cd4
  12. 01 3月, 2012 1 次提交
  13. 25 11月, 2011 2 次提交
  14. 01 11月, 2011 1 次提交
  15. 29 9月, 2011 1 次提交
    • J
      powerpc: Fix xmon for systems without MSR[RI] · 66857b3a
      Jimi Xenidis 提交于
      Based on patch by David Gibson <dwg@au1.ibm.com>
      
      xmon has a longstanding bug on systems which are SMP-capable but lack
      the MSR[RI] bit.  In these cases, xmon invoked by IPI on secondary
      CPUs will not properly keep quiet, but will print stuff, thereby
      garbling the primary xmon's output.  This patch fixes it, by ignoring
      the RI bit if the processor does not support it.
      
      There's already a version of this for 4xx upstream, which we'll need
      to extend to other RI-lacking CPUs at some point.  For now this adds
      Book3e processors to the mix.
      Signed-off-by: NJimi Xenidis <jimix@pobox.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      66857b3a
  16. 19 5月, 2011 1 次提交
    • M
      powerpc: Remove call sites of MSG_ALL_BUT_SELF · e0476371
      Milton Miller 提交于
      The only user of MSG_ALL_BUT_SELF in the whole kernel tree is powerpc,
      and it only uses it to start the debugger. Both debuggers always call
      smp_send_debugger_break with MSG_ALL_BUT_SELF, and only mpic can do
      anything more optimal than a loop over all online cpus, but all message
      passing implementations have to code for this special delivery target.
      
      Convert smp_send_debugger_break to take void and loop calling the smp_ops
      message_pass function for each of the other cpus in the online cpumask.
      
      Use raw_smp_processor_id() because we are either entering the debugger
      or trying to start kdump and the additional warning it not useful were
      it to trigger.
      Signed-off-by: NMilton Miller <miltonm@bga.com>
      Signed-off-by: NBenjamin Herrenschmidt <benh@kernel.crashing.org>
      e0476371
  17. 04 5月, 2011 2 次提交
  18. 27 4月, 2011 2 次提交
  19. 25 3月, 2011 1 次提交
  20. 13 10月, 2010 1 次提交
  21. 20 8月, 2010 1 次提交
  22. 14 7月, 2010 1 次提交
  23. 03 2月, 2010 1 次提交
  24. 24 11月, 2009 1 次提交
  25. 27 10月, 2009 1 次提交
  26. 24 9月, 2009 1 次提交