- 13 12月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Firmware 1.12.25.0 added support for QSA module, adding the driver code for it. Also fixes some ethtool get settings for other module types. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 12月, 2014 1 次提交
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由 Stephen Rothwell 提交于
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 12月, 2014 3 次提交
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由 Hariprasad Shenai 提交于
Use BAR2 Going To Sleep (GTS) for T5 and later. Use new BAR2 User Doorbells for T5 for both cxgb4 and cxgb4vf driver. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Add new Common Code facilities for calculating T5 BAR2 Offsets for SGE Queue Registers. This new code can handle situations where Queues Per Page * SGE BAR2 Queue Register Area Size > Page Size Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 11月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
This patch cleanups all PCIE, RSS & FW related macros/register defines that are defined in t4fw_api.h and the affected files. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 11月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Various patches have ended up changing the style of the symbolic macros/register defines to different style. As a result, the current kernel.org files are a mix of different macro styles. Since this macro/register defines is used by different drivers a few patch series have ended up adding duplicate macro/register define entries with different styles. This makes these register define/macro files a complete mess and we want to make them clean and consistent. This patch cleans up a part of it. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 10月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Use t4_fw_upgrade instead of t4_load_fw to write firmware into FLASH, since t4_load_fw doesn't co-ordinate with the firmware and the adapter can get hosed enough to require a power cycle of the system. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 10月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Call t4_wait_dev_ready() before attempting to read the PL_WHOAMI register (to determine which function we have been attached to). This prevents us from failing on that read if it comes right after a RESET. Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 29 9月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Based on original work by Kumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Use BAR2 GTS for T5. If we are on T4 use the old doorbell mechanism; otherwise ue the new BAR2 mechanism. Use BAR2 doorbells for refilling FL's. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 8月, 2014 1 次提交
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由 Anish Bhatt 提交于
There is a possible race condition when we unregister the PCI Driver and then flush/destroy the global "workq". This could lead to situations where there are tasks on the Work Queue with references to now deleted adapter data structures. Instead, have per-adapter Work Queues which were instantiated and torn down in init_one() and remove_one(), respectively. v2: Remove unnecessary call to flush_workqueue() before destroy_workqueue() Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NCasey Leedom <leedom@chelsio.com> Acked-by: NNeil Horman <nhorman@tuxdriver.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 08 8月, 2014 2 次提交
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由 Anish Bhatt 提交于
* Changes required due to 16eecd9b ("dcbnl : Fix misleading dcb_app->priority explanation") * Driver was previously not aware of what DCBx version was negotiated by firmware, this could lead to DCB app table in kernel or in firmware being populated wrong since IEEE/CEE used different formats made clear by above mentioned commit * Driver was missing a couple of state transitions that could be caused by other drivers that use chelsio hardware, resulting in incorrect behaviour (the change that addresses this also flips the state machine to switch on state instead of transition, hope this is okay in current window) * Prio queue info & tsa is no longer thrown away v2: Print DCBx state transition messages only when debug is enabled Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 05 8月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 16 7月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Advertise a larger max read queue depth for qps, and gather the resource limits from fw and use them to avoid exhaustinq all the resources. Design: cxgb4: Obtain the max_ordird_qp and max_ird_adapter device params from FW at init time and pass them up to the ULDs when they attach. If these parameters are not available, due to older firmware, then hard-code the values based on the known values for older firmware. iw_cxgb4: Fix the c4iw_query_device() to report these correct values based on adapter parameters. ibv_query_device() will always return: max_qp_rd_atom = max_qp_init_rd_atom = min(module_max, max_ordird_qp) max_res_rd_atom = max_ird_adapter Bump up the per qp max module option to 32, allowing it to be increased by the user up to the device max of max_ordird_qp. 32 seems to be sufficient to maximize throughput for streaming read benchmarks. Fail connection setup if the negotiated IRD exhausts the available adapter ird resources. So the driver will track the amount of ird resource in use and not send an RI_WR/INIT to FW that would reduce the available ird resources below zero. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 02 7月, 2014 2 次提交
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由 Hariprasad Shenai 提交于
Rip out a bunch of redundant PCI-E Memory Window Read/Write routines, collapse the more general purpose routines into a single routine thereby eliminating the need for a large stack frame (and extra data copying) in the outer routine, change everything to use the improved routine t4_memory_rw. Based on origninal work by Casey Leedom <leedom@chelsio.com> and Steve Wise <swise@opengridcomputing.com> Signed-off-by: NCasey Leedom <leedom@chelsio.com> Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Use the firmware interface to get the BAR0 value since we really don't want to use the PCI-E Configuration Space Backdoor access which is owned by the firmware. Set up PCI-E Memory Window registers using the true values programmed into BAR registers. When the PF4 "Master Function" is exported to a Virtual Machine, the values returned by pci_resource_start() will be for the synthetic PCI-E Configuration Space and not the real addresses. But we need to program the PCI-E Memory Window address decoders with the real addresses that we're going to be using in order to have accesses through the Memory Windows work. Based on origninal work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NCasey Leedom <leedom@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 6月, 2014 2 次提交
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由 Anish Bhatt 提交于
Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Anish Bhatt 提交于
cxgb4 : Integrate DCBx support into cxgb4 module. Register dbcnl_ops to give access to DCBx functions Signed-off-by: NAnish Bhatt <anish@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 11 6月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Currently indirect interrupts for RDMA CQs funnel through the LLD's RDMA RXQs, which also handle direct interrupts for offload CPLs during RDMA connection setup/teardown. The intended T4 usage model, however, is to have indirect interrupts flow through dedicated IQs. IE not to mix indirect interrupts with CPL messages in an IQ. This patch adds the concept of RDMA concentrator IQs, or CIQs, setup and maintained by the LLD and exported to iw_cxgb4 for use when creating CQs. RDMA CPLs will flow through the LLD's RDMA RXQs, and CQ interrupts flow through the CIQs. Design: cxgb4 creates and exports an array of CIQs for the RDMA ULD. These IQs are sized according to the max available CQs available at adapter init. In addition, these IQs don't need FL buffers since they only service indirect interrupts. One CIQ is setup per RX channel similar to the RDMA RXQs. iw_cxgb4 will utilize these CIQs based on the vector value passed into create_cq(). The num_comp_vectors advertised by iw_cxgb4 will be the number of CIQs configured, and thus the vector value will be the index into the array of CIQs. Based on original work by Steve Wise <swise@opengridcomputing.com> Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 15 3月, 2014 1 次提交
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由 Steve Wise 提交于
The current logic suffers from a slow response time to disable user DB usage, and also fails to avoid DB FIFO drops under heavy load. This commit fixes these deficiencies and makes the avoidance logic more optimal. This is done by more efficiently notifying the ULDs of potential DB problems, and implements a smoother flow control algorithm in iw_cxgb4, which is the ULD that puts the most load on the DB fifo. Design: cxgb4: Direct ULD callback from the DB FULL/DROP interrupt handler. This allows the ULD to stop doing user DB writes as quickly as possible. While user DB usage is disabled, the LLD will accumulate DB write events for its queues. Then once DB usage is reenabled, a single DB write is done for each queue with its accumulated write count. This reduces the load put on the DB fifo when reenabling. iw_cxgb4: Instead of marking each qp to indicate DB writes are disabled, we create a device-global status page that each user process maps. This allows iw_cxgb4 to only set this single bit to disable all DB writes for all user QPs vs traversing the idr of all the active QPs. If the libcxgb4 doesn't support this, then we fall back to the old approach of marking each QP. Thus we allow the new driver to work with an older libcxgb4. When the LLD upcalls iw_cxgb4 indicating DB FULL, we disable all DB writes via the status page and transition the DB state to STOPPED. As user processes see that DB writes are disabled, they call into iw_cxgb4 to submit their DB write events. Since the DB state is in STOPPED, the QP trying to write gets enqueued on a new DB "flow control" list. As subsequent DB writes are submitted for this flow controlled QP, the amount of writes are accumulated for each QP on the flow control list. So all the user QPs that are actively ringing the DB get put on this list and the number of writes they request are accumulated. When the LLD upcalls iw_cxgb4 indicating DB EMPTY, which is in a workq context, we change the DB state to FLOW_CONTROL, and begin resuming all the QPs that are on the flow control list. This logic runs on until the flow control list is empty or we exit FLOW_CONTROL mode (due to a DB DROP upcall, for example). QPs are removed from this list, and their accumulated DB write counts written to the DB FIFO. Sets of QPs, called chunks in the code, are removed at one time. The chunk size is 64. So 64 QPs are resumed at a time, and before the next chunk is resumed, the logic waits (blocks) for the DB FIFO to drain. This prevents resuming to quickly and overflowing the FIFO. Once the flow control list is empty, the db state transitions back to NORMAL and user QPs are again allowed to write directly to the user DB register. The algorithm is designed such that if the DB write load is high enough, then all the DB writes get submitted by the kernel using this flow controlled approach to avoid DB drops. As the load lightens though, we resume to normal DB writes directly by user applications. Signed-off-by: NSteve Wise <swise@opengridcomputing.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 3月, 2014 2 次提交
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由 Kumar Sanghvi 提交于
Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Kumar Sanghvi 提交于
Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 19 2月, 2014 3 次提交
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由 Kumar Sanghvi 提交于
Query firmware to see whether we're allowed to use T5 ULPTX MEMWRITE DSGL capabilities. Also pass that information to Upper Layer Drivers via the new (struct cxgb4_lld_info).ulptx_memwrite_dsgl boolean. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Kumar Sanghvi 提交于
When we attach to adapter, print VPD Part Number instead of Engineering Change field. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Kumar Sanghvi 提交于
Also, create a new Common Code interface to translate Firmware Port Technology Type values (enum fw_port_type) to string descriptions. This will allow us to maintain the description translation table in one place rather than in every driver. Based on original work by Scott Bardone and Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 24 1月, 2014 1 次提交
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由 Gavin Shan 提交于
If we have EEH error happens to the adapter and we have to remove it from the system for some reasons (e.g. more than 5 EEH errors detected from the device in last hour), the adapter will be disabled for towice separately by eeh_err_detected() and remove_one(), which will incur following unexpected backtrace. The patch tries to avoid it. WARNING: at drivers/pci/pci.c:1431 CPU: 12 PID: 121 Comm: eehd Not tainted 3.13.0-rc7+ #1 task: c0000001823a3780 ti: c00000018240c000 task.ti: c00000018240c000 NIP: c0000000003c1e40 LR: c0000000003c1e3c CTR: 0000000001764c5c REGS: c00000018240f470 TRAP: 0700 Not tainted (3.13.0-rc7+) MSR: 8000000000029032 <SF,EE,ME,IR,DR,RI> CR: 28000024 XER: 00000004 CFAR: c000000000706528 SOFTE: 1 GPR00: c0000000003c1e3c c00000018240f6f0 c0000000010fe1f8 0000000000000035 GPR04: 0000000000000000 0000000000000000 00000000003ae509 0000000000000000 GPR08: 000000000000346f 0000000000000000 0000000000000000 0000000000003fef GPR12: 0000000028000022 c00000000ec93000 c0000000000c11b0 c000000184ac3e40 GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR20: 0000000000000000 0000000000000000 0000000000000000 0000000000000000 GPR24: 0000000000000000 c0000000009398d8 c00000000101f9c0 c0000001860ae000 GPR28: c000000182ba0000 00000000000001f0 c0000001860ae6f8 c0000001860ae000 NIP [c0000000003c1e40] .pci_disable_device+0xd0/0xf0 LR [c0000000003c1e3c] .pci_disable_device+0xcc/0xf0 Call Trace: [c0000000003c1e3c] .pci_disable_device+0xcc/0xf0 (unreliable) [d0000000073881c4] .remove_one+0x174/0x320 [cxgb4] [c0000000003c57e0] .pci_device_remove+0x60/0x100 [c00000000046396c] .__device_release_driver+0x9c/0x120 [c000000000463a20] .device_release_driver+0x30/0x60 [c0000000003bcdb4] .pci_stop_bus_device+0x94/0xd0 [c0000000003bcf48] .pci_stop_and_remove_bus_device+0x18/0x30 [c00000000003f548] .pcibios_remove_pci_devices+0xa8/0x140 [c000000000035c00] .eeh_handle_normal_event+0xa0/0x3c0 [c000000000035f50] .eeh_handle_event+0x30/0x2b0 [c0000000000362c4] .eeh_event_handler+0xf4/0x1b0 [c0000000000c12b8] .kthread+0x108/0x130 [c00000000000a168] .ret_from_kernel_thread+0x5c/0x74 Signed-off-by: NGavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 10 1月, 2014 1 次提交
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 23 12月, 2013 2 次提交
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由 stephen hemminger 提交于
Cleanup by making local functions static. The code to load config file is unreachable in net-next, probably came from some out of tree driver. Signed-off-by: NStephen Hemminger <stephen@networkplumber.org> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Kumar Sanghvi 提交于
Adds API cxgb4_select_ntuple so as to enable Upper Level Drivers to correctly calculate the tuple fields. Adds constant definitions for TP_VLAN_PRI_MAP for the Compressed Filter Tuple field widths and structures and uses them. Also, the CPL Parameters field for T5 is 40 bits so we need to prototype cxgb4_select_ntuple() to calculate and return u64 values. Based on original work by Casey Leedom <leedom@chelsio.com> Signed-off-by: NKumar Sanghvi <kumaras@chelsio.com> Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 04 12月, 2013 2 次提交
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Hariprasad Shenai 提交于
Signed-off-by: NHariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 22 10月, 2013 1 次提交
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由 Michael Opdenacker 提交于
Reported by "make includecheck" Tested that C sources including this file still compile well on x86 Signed-off-by: NMichael Opdenacker <michael.opdenacker@free-electrons.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 13 8月, 2013 1 次提交
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由 Vipul Pandya 提交于
The Compressed LIP region is used to hold a limited number of Local IPv6 addresses. This region is primarily used to reduce the TCAM space consumed for an IPv6 offloaded connection. A 128-bit LIP will be reduced to 13-bit and stored in the TCAM if there is a match between the IPv6 tuple's LIP and the one stored in the CLIP region. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NRoland Dreier <roland@purestorage.com>
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- 01 6月, 2013 1 次提交
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由 Jay Hernandez 提交于
Forcing uninitialized state allows us to upgrade and reinitialize the adapter. FW_VERSION_T4 = 1.4.0.0 FW_VERSION_T5 = 0.0.0.0 At this point driver supports above and greater than above version of firmware. If it doesn't find the required firmware version than it forces the adapter to be reinitialized as shown below. 1) If FW_ON_ADAPTER < FW_VERSION and we're the MASTER_PF force uninitialized state and a FW upgrade if available. - If FW_ON_ADAPTER < /lib/firmware/cxgb4/t*fw.bin we will update the adapters FW. - If FW_ON_ADAPTER >= /lib/firmware/cxgb4/t*fw.bin don't upgrade FW. - If upgrade_fw() fails force reinitialization of the adapter anyways, it might still work. Either way forcing the uninitialized state allows cxgb4 reinitialize FW. 2) If FW_ON_ADAPTER >= FW_VERSION driver follows normal path. Signed-off-by: NJay Hernandez <jay@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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- 14 3月, 2013 3 次提交
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由 Santosh Rastapur 提交于
All T5 adapters will only support VFs on PF0-3 despite the ability of the hardware to support them on PF4-7. This keeps our T4 and T5 adapters more similar which simplifies host driver software. Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Santosh Rastapur 提交于
Signed-off-by: NSantosh Rastapur <santosh@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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由 Santosh Rastapur 提交于
This patch implements a low latency Write Combining (aka Write Coalescing) work request path. PCIE maps User Space Doorbell BAR2 region writes to the new interface to SGE. SGE pulls a new message from PCIE new interface and if its a coalesced write work request then pushes it for processing. This patch copies coalesced work request to memory mapped BAR2 space. Signed-off-by: NSantosh Rastapur <santosh@chelsio.com> Signed-off-by: NVipul Pandya <vipul@chelsio.com> Signed-off-by: NDavid S. Miller <davem@davemloft.net>
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