On some ARM based systems, a separate Cortex-M based System Control
Processor(SCP) provides the overall power, clock, reset and system
control. System Control and Power Interface(SCPI) Message Protocol
is defined for the communication between the Application Cores(AP)
and the SCP.

This patch adds support for the clocks provided by SCP using SCPI
protocol.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Cc: Mike Turquette <mturquette@baylibre.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>
Cc: linux-clk@vger.kernel.org

Commit d5e136a2 ("clk: samsung: Register
clk provider only after registering its all clocks", merged to v3.17-rc1)
modified a way that driver registers registers to core framework. This
change has not been applied to s5pv210 clocks driver, which has been
merged in parallel to that commit. This patch adds a missing call to
samsung_clk_of_add_provider(), so the driver is operational again.
Signed-off-by: NMarek Szyprowski <m.szyprowski@samsung.com>
CC: stable@vger.kernel.org  # v3.17+
Acked-by: NTomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

Current critical clock list for pistachio enables
only mips and sys clocks by default but there are
also other clocks that are not claimed by anyone and
needs to be enabled by default.

This patch updates the critical clocks that need
to be enabled by default.

Add a separate struct to distinguish the critical clocks
as listed:
1.) core clocks:
	a.) mips clock
2.) peripheral system clocks:
	a.) sys clock
	b.) sys_bus clock
	c.) DDR clock
	d.) ROM clock

Fixes: b35d7c33("CLK: Pistachio: Register core clocks")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NEzequiel Garcia <ezequiel.garcia@imgtec.com>
Signed-off-by: NDamien.Horsley <Damien.Horsley@imgtec.com>
Signed-off-by: NGovindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

.recalc_rate callback for the fractional PLL doesn't take operating
mode into account when calculating PLL rate. This results in
the incorrect PLL rates when PLL is operating in integer mode.

Operating mode of fractional PLL is based on the value of the
fractional divider. Currently it assumes that the PLL will always
be configured in fractional mode which may not be
the case. This may result in the wrong output frequency.

Also vco was calculated based on the current operating mode which
makes no sense because .set_rate is setting operating mode. Instead,
vco should be calculated using PLL settings that are about to be set.

Fixes: 43049b0c("CLK: Pistachio: Add PLL driver")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NZdenko Pulitika <zdenko.pulitika@imgtec.com>
Signed-off-by: NGovindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PLL enable callbacks are overriding PLL mode (int/frac) and
Noise reduction (on/off) settings set by the boot loader which
results in the incorrect clock rate.

PLL mode and noise reduction are defined by the DSMPD and DACPD bits
of the PLL control register. PLL .enable() callbacks enable PLL
by deasserting all power-down bits of the PLL control register,
including DSMPD and DACPD bits, which is not necessary since
these bits don't actually enable/disable PLL.

This commit fixes the problem by removing DSMPD and DACPD bits
from the "PLL enable" mask.

Fixes: 43049b0c("CLK: Pistachio: Add PLL driver")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: NAndrew Bresitcker <abrestic@chromium.org>
Signed-off-by: NZdenko Pulitika <zdenko.pulitika@imgtec.com>
Signed-off-by: NGovindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This commit fixes 32bit integer overflows throughout the pll driver
(i.e. wherever the result of integer multiplication may exceed the
range of u32).

One of the functions affected by this problem is .recalc_rate. It
returns incorrect rate for some pll settings (not for all though)
which in turn results in the incorrect rate setup of pll's child
clocks.

Fixes: 43049b0c("CLK: Pistachio: Add PLL driver")
Cc: <stable@vger.kernel.org> # 4.1
Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
Signed-off-by: NZdenko Pulitika <zdenko.pulitika@imgtec.com>
Signed-off-by: NGovindraj Raja <govindraj.raja@imgtec.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The latest Tegra clk pull had some problems. Fix them.

drivers/clk/tegra/clk-tegra124.c:1450:6: warning: symbol 'tegra124_clock_assert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1466:6: warning: symbol 'tegra124_clock_deassert_dfll_dvco_reset' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1476:5: warning: symbol 'tegra124_reset_assert' was not declared. Should it be static?
drivers/clk/tegra/clk-tegra124.c:1486:5: warning: symbol 'tegra124_reset_deassert' was not declared. Should it be static?
drivers/clk/tegra/clk-dfll.c:590 dfll_load_i2c_lut() warn: inconsistent indenting
drivers/clk/tegra/clk-dfll.c:1448 dfll_build_i2c_lut() warn: unsigned 'td->i2c_lut[0]' is never less than zero.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Fix the enable bit of the pseudorandom number generator clock.
Reported-by: NStanimir Varbanov <stanimir.varbanov@linaro.org>
Fixes: 3966fab8 "clk: qcom: Add MSM8916 Global Clock Controller support"
Signed-off-by: NGeorgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Init data marked const should be annotated with __initconst for
correctness and not __initdata.  This also fixes LTO builds that
otherwise fail with section mismatch errors.
Signed-off-by: NNicolas Pitre <nico@linaro.org>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>
[sboyd@codeaurora.org: Dropped hunks that moved const char *
arrays to const char * const]
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The structure is xin24m -> pll -> pll-mux (xin24m,pll,xin32k). The pll
does have an init callback to make sure the boot-selected frequency is
using the expected pll settings and resets the same frequency using
the values provided in the driver if necessary.

The setting itself also involves remuxing the pll-mux temporarily to
the xin24m source to let the new pll rate settle. Until now this worked
flawlessly, even when it had the flaw of accessing the mux settings
before the mux actually got registered.

With the recent clock-core conversions this flaw became apparent in
null pointer dereference in
[<c03fc400>] (clk_hw_get_num_parents) from [<c0400df0>] (clk_mux_get_parent+0x14/0xc8)
[<c0400ddc>] (clk_mux_get_parent) from [<c040246c>] (rockchip_rk3066_pll_set_rate+0xd8/0x320)

So to fix that, simply register the pll-mux before the pll, so that
it will be fully initialized when the pll clock executes its init-
callback and possibly touches the pll-mux clock.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NMichael Turquette <mturquette@baylibre.com>

The base addresses for the Ux500 PRCC controllers are hardcoded,
let's move them to the clock node in the device tree and delete
the constants.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Acked-by: NOlof Johansson <olof@lixom.net>
Acked-by: NMichael Turquette <mturquette@baylibre.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

__clk_set_parent_after() actually used the second argument then we
could put this duplicate logic in there and call it with a different
order of arguments in the success vs. error paths in this function.

Cc: Mike Turquette <mturquette@linaro.org>
Suggested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NDong Aisheng <aisheng.dong@freescale.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Use the provider based method to get a clock's name so that we
can get rid of the clk member in struct clk_hw one day. Mostly
converted with the following coccinelle script.

@@
struct clk_hw *E;
@@

-__clk_get_name(E->clk)
+clk_hw_get_name(E)
Acked-by: NHeiko Stuebner <heiko@sntech.de>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: NThierry Reding <treding@nvidia.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: NAndrew Bresticker <abrestic@chromium.org>
Cc: Ezequiel Garcia <ezequiel.garcia@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Kevin Cernekee <cernekee@chromium.org>
Acked-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Cc: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-rockchip@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We don't modify the clk_hw argument in these functions, so it's
safe to mark it as const.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

On Hi6220, there have some clocks which can use mailbox channel to send
messages to power controller to change frequency; this includes CPU, GPU
and DDR clocks.

For dynamic frequency scaling, firstly need write the frequency value to
SRAM region, and then send message to mailbox to trigger power controller
to handle this requirement. This driver will use syscon APIs to pass SRAM
memory region and use common mailbox APIs for channels accessing.

This init driver will support cpu frequency change firstly.
Signed-off-by: NLeo Yan <leo.yan@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

PLL VCO frequency is given by Fvco = Fref * 2 * NF / NR
in integer-N mode, or by Fvco = Fref * SSN / NR in Spread
Spectrum (fractional-N) mode. Thus fix the missing part
of NR
Signed-off-by: NGuo Zeng <guo.zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

bit4 thcpum_cpudiv4_clken 	r/w
thcpum_cpudiv4_clk clock enable (default: 1)
Root clock CPU_CLK must be enabled for this clock to be enabled

bit3 coresight_tpiu_clken 	r/w
coresight_tpiu_clk clock enable (default: 0)
Root clock TPIU_CLK must be enabled for this clock to be enabled
Signed-off-by: NGuo Zeng <guo.zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NYibo Cai <yibo.cai@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

I cannot believe that I spend quite a lot time in finding this bug.
It seems a pitfall people tend to fall in.

In "int64 = int32 * int32", conversion from 32-bits to 64-bits comes
after the multiplication. So this statement may not work as expected.
Signed-off-by: NYibo Cai <yibo.cai@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

this patch makes mux clks can be referenced by device drivers.
Signed-off-by: NGuo Zeng <guo.zeng@csr.com>
Signed-off-by: NBarry Song <Barry.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Signed-off-by: NGuo Zeng <Guo.Zeng@csr.com>
Signed-off-by: NBarry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

The debug base clock can be bypassed from the main PLL to the OSC1 clock.
The bypass register is the staysoc1(0x10) register that is in the clock
manager.

This patch adds the option to get the correct parent for the debug base
clock.
Signed-off-by: NDinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This code is unused and not coming back. Let's kill it off.

Cc: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

Remove these APIs now that we've converted all users to the
replacement struct clk_hw based versions.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

This driver uses __clk_get_name() when it's dealing with struct
clk_hw pointers. Use the simpler form so that we can get rid of
the clk member in struct clk_hw one day.
Acked-by: NSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API. This code is
calling the consumer APIs to change the parent to a 1 MHz fixed
rate clock for each of the clocks that the driver provides. Move
to using the assigned-clock-parents DT property for this instead.
Because this is an ABI break, detect if the property is missing
and fall back to setting the parent explicitly before the clocks
are registered.
Acked-by: NPawel Moll <pawel.moll@arm.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Tested-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Acked-by: NTero Kristo <t-kristo@ti.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Thierry Reding <treding@nvidia.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: "Emilio López" <emilio@elopez.com.ar>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Acked-by: NViresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: NSylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Reviewed-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Daniel Thompson <daniel.thompson@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs. This also
removes a clk_get() in this driver that can just as easily use
of_clk_get_parent_name() instead.

Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.

Cc: Chao Xie <chao.xie@marvell.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Reviewed-by: NAlex Elder <elder@linaro.org>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

We're removing struct clk from the clk provider API, so switch
this code to using the clk_hw based provider APIs.
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>