Skip to content

cloud-kernel
cloud-kernel

openanolis / cloud-kernel
1 年多 前同步成功

通知 160
Star 36
Fork 7
cloud-kernel
cloud-kernel
切换分支/标签
  1. 27 9月, 2016 6 次提交
  3. 12 7月, 2016 1 次提交
  5. 08 7月, 2016 2 次提交
  7. 13 5月, 2016 1 次提交
  9. 03 5月, 2016 1 次提交
  11. 06 4月, 2016 1 次提交
    • K
      dmaengine: vdma: Add 64 bit addressing support to the driver · b72db400
      由 Kedareswara rao Appana 提交于 
      This VDMA  is a soft ip, which can be programmed to support
32 bit addressing or greater than 32 bit addressing.

When the VDMA ip is configured for 32 bit address space
the buffer address is specified by a single register
(0x5C for MM2S and 0xAC for S2MM channel).

When the  VDMA core is configured for an address space greater
than 32 then each buffer address is specified by a combination of
two registers.

The first register specifies the LSB 32 bits of address,
while the next register specifies the MSB 32 bits of address.

For example, 5Ch will specify the LSB 32 bits while 60h will
specify the MSB 32 bits of the first start address.
So we need to program two registers at a time.

This patch adds the 64 bit addressing support to the vdma driver.
Signed-off-by: NAnurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: NKedareswara rao Appana <appanad@xilinx.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      b72db400
  13. 11 3月, 2016 1 次提交
  15. 22 2月, 2016 1 次提交
  17. 21 11月, 2015 1 次提交
    • A
      ASoC: samsung: pass filter function as pointer · 9bdca822
      由 Arnd Bergmann 提交于 
      As we are now passing the filter data as pointers to the drivers,
we can take the final step and also pass the filter function the
same way. I'm keeping this change separate, as there it's less
obvious that this is a net win.

Upsides of this are:

- The ASoC drivers are completely independent from the DMA engine
  implementation, which simplifies the Kconfig logic and in theory
  allows the same sound drivers to be built in a kernel that supports
  different kinds of dmaengine drivers.

- Consistency with other subsystems and drivers

On the other hand, we have a few downsides:

- The s3c24xx-dma driver now needs to be built-in for the ac97 platform
  device to be instantiated on s3c2440.

- samsung_dmaengine_pcm_config cannot be marked 'const' any more
  because the filter function pointer needs to be set at runtime.
  This is safe as long we don't have multiple different DMA engines
  in thet same system at runtime, but is nonetheless ugly.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Reviewed-by: NKrzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: NMark Brown <broonie@kernel.org>
      9bdca822
  19. 16 11月, 2015 1 次提交
  21. 27 10月, 2015 1 次提交
  23. 14 10月, 2015 1 次提交
  25. 24 9月, 2015 1 次提交
  27. 24 8月, 2015 1 次提交
  29. 23 8月, 2015 1 次提交
    • L
      dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller · 0e3b67b3
      由 Lars-Peter Clausen 提交于 
      Add support for the Analog Devices AXI-DMAC DMA controller. This controller
is a soft peripheral that can be instantiated in a FPGA and is often used
in Analog Devices' reference designs for FPGA platforms.

The peripheral has various configuration options that can be selected at
synthesis time and influence the supported features of the instantiated
peripheral, those options are represented as device-tree properties to
allow the driver to behave accordingly.

The peripheral has a zero latency architecture, which means it is possible
to switch from one to the next descriptor without any delay. This is
archived by having a internal queue which can hold multiple descriptors.
The driver supports this, which means it will submit new descriptors
directly to the hardware until the queue is full and not wait for a
descriptor to complete before the next one is submitted. Interrupts are
used for the descriptor queue flow control.

Currently the driver supports SG, cyclic and interleaved slave DMA.
Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      0e3b67b3
  31. 21 8月, 2015 1 次提交
    • D
      dmaengine: ioatdma: fix zero day warning on incompatible pointer type · aaecdebc
      由 Dave Jiang 提交于 
      The 32bit build is creating this warning. Since we don't expect anyone
actually use this on 32bit, restrict ioatdma to be built only on x86_64.
This issue has long existed and only reason it's surfacing due to code
refactoring.

   drivers/dma/ioat/dma.c: In function 'ioat_timer_event':
>> drivers/dma/ioat/dma.c:870:39: warning: passing argument 2 of 'ioat_cleanup_preamble' from incompatible pointer type
     if (ioat_cleanup_preamble(ioat_chan, &phys_complete))
                                          ^
   drivers/dma/ioat/dma.c:577:13: note: expected 'u64 *' but argument is of type 'dma_addr_t *'
    static bool ioat_cleanup_preamble(struct ioatdma_chan *ioat_chan,
                ^
Signed-off-by: NDave Jiang <dave.jiang@intel.com>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      aaecdebc
  33. 20 8月, 2015 1 次提交
  35. 19 8月, 2015 1 次提交
  37. 28 7月, 2015 1 次提交
  39. 16 7月, 2015 1 次提交
  41. 26 5月, 2015 1 次提交
    • R
      dmaengine: pxa: add pxa dmaengine driver · a57e16cf
      由 Robert Jarzmik 提交于 
      This is a new driver for pxa SoCs, which is also compatible with the former
mmp_pdma.

The rationale behind a new driver (as opposed to incremental patching) was :

 - the new driver relies on virt-dma, which obsoletes all the internal
   structures of mmp_pdma (sw_desc, hw_desc, ...), and by consequence all the
   functions

 - mmp_pdma allocates dma coherent descriptors containing not only hardware
   descriptors but linked list information
   The new driver only puts the dma hardware descriptors (ie. 4 u32) into the
   dma pool allocated memory. This changes completely the way descriptors are
   handled

 - the architecture behind the interrupt/tasklet management was rewritten to be
   more conforming to virt-dma

 - the buffers alignment is handled differently
   The former driver assumed that the DMA channel stopped between each
   descriptor. The new one chains descriptors to let the channel running. This
   is a necessary guarantee for real-time high bandwidth usecases such as video
   capture on "old" architectures such as pxa.

 - hot chaining / cold chaining / no chaining
   Whenever possible, submitting a descriptor "hot chains" it to a running
   channel. There is still no guarantee that the descriptor will be issued, as
   the channel might be stopped just before the descriptor is submitted. Yet
   this allows to submit several video buffers, and resubmit a buffer while
   another is under handling.
   As before, dma_async_issue_pending() is the only guarantee to have all the
   buffers issued.
   When an alignment issue is detected (ie. one address in a descriptor is not
   a multiple of 8), if the already running channel is in "aligned mode", the
   channel will stop, and restarted in "misaligned mode" to finished the issued
   list.

 - descriptors reusing
   A submitted, issued and completed descriptor can be reused, ie resubmitted if
   it was prepared with the proper flag (DMA_PREP_ACK).  Only a channel
   resources release will in this case release that buffer.
   This allows a rolling ring of buffers to be reused, where there are several
   thousands of hardware descriptors used (video buffer for example).

Additionally, a set of more casual features is introduced :
 - debugging traces
 - lockless way to know if a descriptor is terminated or not

The driver was tested on zylonite board (pxa3xx) and mioa701 (pxa27x),
with dmatest, pxa_camera and pxamci.
Signed-off-by: NRobert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
      a57e16cf
  43. 14 5月, 2015 1 次提交
  45. 27 4月, 2015 1 次提交
  47. 02 4月, 2015 2 次提交
  49. 01 4月, 2015 1 次提交
  51. 17 3月, 2015 1 次提交
  53. 07 3月, 2015 1 次提交
  55. 05 2月, 2015 1 次提交
  57. 24 1月, 2015 1 次提交
  59. 17 11月, 2014 2 次提交
  61. 06 11月, 2014 1 次提交
  63. 28 9月, 2014 1 次提交