- 20 3月, 2014 9 次提交
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由 Jean-Jacques Hiblot 提交于
The PCKRDY bit is not set until the system clock is enabled. This patch moves the management of the ready status in the system clock driver. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NJean-Jacques Hiblot <jjhiblot@traphandler.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Boris BREZILLON 提交于
System clks are just gates, and thus do not provide any rate operations. Authorize clk rate change to be propagated to system clk parents. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Boris BREZILLON 提交于
Implement the determine_rate callback to choose the best parent clk that fulfills the requested rate. Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Laurent Pinchart 提交于
Briefly document the common clock framework locking scheme from a clock driver point of view. Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
Merge tag 'clk-hisi' of https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilcon updating clock drivers for Hisilicon
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由 Emilio López 提交于
This should read MOD0 and not MMC; MMC is just one example of a MOD0 clock. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Emilio López 提交于
Some divisor calculations were misrounded, causing higher than requested rates on some clocks. Fix them up using DIV_ROUND_UP, and replace one homebrew instance of it as well with the right macro. Reported-by: NBoris BREZILLON <b.brezillon.dev@gmail.com> Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Emilio López 提交于
Allwinner actually reworked the PLL4 on A20; now it's compatible with the sun4i PLL5/6 design previous to any divisions, as well as to the new PLL8 in sun7i. Signed-off-by: NEmilio López <emilio@elopez.com.ar> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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https://bitbucket.org/emiliolopez/linux由 Mike Turquette 提交于
Allwinner sunXi SoCs clock changes This adds support for the new, more correct clock node naming and gets the A10 compatibles in line with the rest of the other SoCs. It also adds support for the USB, GMAC and A31's PLL6 clocks. Some of these changes also require DT modifications that will be merged via arm-soc.
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- 19 3月, 2014 8 次提交
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由 Haojian Zhuang 提交于
Remove the static variable. So these common clock register helper could be used in more SoCs. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Haojian Zhuang 提交于
Now only fixed rate clocks are appended into the clock driver. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Haojian Zhuang 提交于
The fixed rate and fixed factor clock isn't registered to clk table. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org>
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由 Dinh Nguyen 提交于
WARNING: drivers/clk/socfpga/built-in.o(.data+0xc0): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_pll_init() The variable socfpga_child_clocks references the function __init socfpga_pll_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x184): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_periph_init() The variable socfpga_child_clocks references the function __init socfpga_periph_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console WARNING: drivers/clk/socfpga/built-in.o(.data+0x248): Section mismatch in reference from the variable socfpga_child_clocks to the function .init.text:socfpga_gate_init() The variable socfpga_child_clocks references the function __init socfpga_gate_init() If the reference is valid then annotate the variable with __init* or __refdata (see linux/init.h) or name the variable: *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console Reported-by: NMike Turquette <mturquette@linaro.org> Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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git://git.infradead.org/linux-mvebu由 Mike Turquette 提交于
clock: mvebu new SoC changes for v3.15 (incremental pull #2) - mvebu (Armada 375) - fix ratio register offest - mvebu (Armada 380) - expand core divider clock driver to support 380 SoC (enables nand support)
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由 Tushar Behera 提交于
Since clock operation within S2MPS11 and S5M8767 are similar, we can support both the devices within a single driver. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tushar Behera 提交于
The clocks in S2MPS11 and S5M8767 are managed in the same way, baring a difference in the register offset. It would be better to update existing S2MPS11 driver to support the clocks in S5M8767, rather than creating an almost duplicate driver altogether. Signed-off-by: NTushar Behera <tushar.behera@linaro.org> Reviewed-by: NTomasz Figa <t.figa@samsung.com> Reviewed-by: NYadwinder Singh Brar <yadi.brar@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jonas Jensen 提交于
MOXA ART SoCs allow to determine PLL output and APB frequencies by reading registers holding multiplier and divisor information. Add a clock driver for this SoC. Signed-off-by: NJonas Jensen <jonas.jensen@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 14 3月, 2014 3 次提交
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由 Ezequiel Garcia 提交于
The Core Divider clock support two new compatible strings for Armada 375 and Armada 380 SoCs. Add the compatible strings to the documentation. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-7-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
This commit adds support for the Core Divider clocks of the Armada 380 SoCs. Similarly to Armada 370 and XP, the Core Divider clocks of the 380 have gate capabilities. The only difference is the register layout. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394742273-5113-2-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Ezequiel Garcia 提交于
This commit fixes the ratio register offset which is 0x4, as per the Armada 375 SoC specification. Signed-off-by: NEzequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1394638901-13368-2-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 27 2月, 2014 9 次提交
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由 Mike Turquette 提交于
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由 Tomi Valkeinen 提交于
ti/clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the ti/clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Tomi Valkeinen 提交于
clk-divider.c does not calculate the rates consistently at the moment. As an example, on OMAP3 we have a clock divider with a source clock of 864000000 Hz. With dividers 6, 7 and 8 the theoretical rates are: 6: 144000000 7: 123428571.428571... 8: 108000000 Calling clk_round_rate() with the rate in the first column will give the rate in the second column: 144000000 -> 144000000 143999999 -> 123428571 123428572 -> 123428571 123428571 -> 108000000 Note how clk_round_rate() returns 123428571 for rates from 123428572 to 143999999, which is mathematically correct, but when clk_round_rate() is called with 123428571, the returned value is surprisingly 108000000. This means that the following code works a bit oddly: rate = clk_round_rate(clk, 123428572); clk_set_rate(clk, rate); As clk_set_rate() also does clock rate rounding, the result is that the clock is set to the rate of 108000000, not 123428571 returned by the clk_round_rate. This patch changes the clk-divider.c to use DIV_ROUND_UP when calculating the rate. This gives the following behavior which fixes the inconsistency: 144000000 -> 144000000 143999999 -> 123428572 123428572 -> 123428572 123428571 -> 108000000 Signed-off-by: NTomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Masanari Iida 提交于
cppcheck detected following error [clk-master.c:245]: (error) Memory leak: characteristics The original code forgot to free characteristics when irq_of_parse_and_map() failed. Signed-off-by: NMasanari Iida <standby24x7@gmail.com> Acked-by Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: NAlexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Lars-Peter Clausen 提交于
This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: NLars-Peter Clausen <lars@metafoo.de>
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由 Zhangfei Gao 提交于
Suggest by Arnd: abstract mmc tuning as clock behavior, also because different soc have different tuning method and registers. hi3620_mmc_clks is added to handle mmc clock specifically on hi3620. Signed-off-by: NZhangfei Gao <zhangfei.gao@linaro.org> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NJaehoon Chung <jh80.chung@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Dinh Nguyen 提交于
The PLLs can be from 3 different sources: osc1, osc2, or the f2s_ref_clk. Update the clock driver to be able to get the correct parent. Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Dinh Nguyen 提交于
Use 64-bit integer for calculating clock rate. Also use do_div for the 64-bit division. Signed-off-by: NGraham Moore <grmoore@altera.com> Signed-off-by: NDinh Nguyen <dinguyen@altera.com> Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Linus Walleij 提交于
The Nomadik debugfs screws up multiplatform boots if debugfs is enabled on the multiplatform image, since it's a simple initcall that is unconditionally executed and reads from certain memory locations. Fix this by checking that the driver has been properly initialized, so a base offset to the Nomadik SRC controller exists, before proceeding to register debugfs files. Reported-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NAndrew Lunn <andrew@lunn.ch> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 2月, 2014 1 次提交
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由 Michal Simek 提交于
Do not use readl/writel directly because the whole clk subsystem is using clk_readl/clk_writel functions. Signed-off-by: NMichal Simek <michal.simek@xilinx.com> Acked-by: NSoren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 25 2月, 2014 8 次提交
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由 Wolfram Sang 提交于
These variable clocks have nothing to do with MSTP gating, probably a copy&paste leftover. Signed-off-by: NWolfram Sang <wsa@sang-engineering.com> Acked-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
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由 Nishanth Menon 提交于
cpu0 clock node has no functionality, since cpufreq-cpu0 is already capable of picking up the clock from dts. Signed-off-by: NNishanth Menon <nm@ti.com> Acked-by: NTero Kristo <t-kristo@ti.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Sylwester Nawrocki 提交于
Ensure clk->kref is dereferenced only when clk is not NULL. Signed-off-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: NSachin Kamat <sachin.kamat@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Jean-Francois Moine 提交于
At probe time, a clock device may not be ready when some other device wants to use it. This patch lets the functions clk_get/devm_clk_get return a probe defer when the clock is defined in the DT but not yet available. Signed-off-by: NJean-Francois Moine <moinejf@free.fr> Reviewed-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: NSylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
Both the pr_err and the additional kerneldoc aim to help when debugging errors thrown from within a clock rate-change notifier callback. Reported-by: NSören Brinkmann <soren.brinkmann@xilinx.com> Acked-by: NSören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Mike Turquette 提交于
Merge branch 'clk-tegra-more-fixes-3.14' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-fixes Fixes stray access to undefined registers, use of wrong clock parents & running clocks at wrong rates. All of these issues cause regressions in the form of boards that are unable to boot or crash and die horrible deaths.
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- 24 2月, 2014 2 次提交
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由 Laurent Pinchart 提交于
The DT bindings document a renesas,indices property, while the code, the DT example and the DT sources all use renesas,clock-indices. Fix the documentation. The shmobile mstp DT bindings have been merged in v3.14-rc1 with a bug in the DT ABI, a fix during the -rc series is appropriate. Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: NSimon Horman <horms@verge.net.au>
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由 Laurent Pinchart 提交于
The qspi clock divisor is incorrectly set to twice the value it should have, possibly because it has been computed based on PLL1 as the clock parent instead of PLL1 / 2 (the datasheets specifies the qspi nominal frequencies, not the divisor values). Fix it. This bug introduced in v3.14-rc1 breaks various devices on the Lager and Kolesh shmobile boards and should thus be considered as a regression for which a fix during the -rc series is appropriate. Reported-by: NGeert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: NLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: NSimon Horman <horms+renesas@verge.net.au>
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