1. 07 12月, 2016 1 次提交
  2. 02 12月, 2016 1 次提交
  3. 19 11月, 2016 1 次提交
  4. 18 11月, 2016 1 次提交
  5. 17 11月, 2016 2 次提交
  6. 11 11月, 2016 1 次提交
  7. 02 11月, 2016 1 次提交
  8. 01 11月, 2016 1 次提交
  9. 29 10月, 2016 3 次提交
  10. 14 10月, 2016 4 次提交
  11. 22 8月, 2016 1 次提交
  12. 17 8月, 2016 1 次提交
  13. 15 8月, 2016 1 次提交
  14. 11 8月, 2016 1 次提交
  15. 05 8月, 2016 1 次提交
  16. 04 8月, 2016 3 次提交
  17. 20 7月, 2016 1 次提交
  18. 15 7月, 2016 1 次提交
  19. 04 7月, 2016 1 次提交
  20. 08 6月, 2016 1 次提交
  21. 11 5月, 2016 1 次提交
  22. 25 4月, 2016 1 次提交
  23. 19 4月, 2016 1 次提交
    • J
      drm/i915: Clean up PCI config register handling · e10fa551
      Joonas Lahtinen 提交于
      Do not use magic numbers, do not prefix stuff with "PCI_", do not
      declare registers in implementation files. Also move the PCI
      registers under correct comment in i915_reg.h.
      
      v2:
      - Consistently use BSM (not BDSM or other variants from PRM) (Chris)
      - Also include register address to help identify the register (Chris)
      v3:
      - Refer to register value as *_val instead of *_reg (Chris)
      v4:
      - Make style checker happy
      
      Cc: Jani Nikula <jani.nikula@intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      e10fa551
  24. 31 3月, 2016 1 次提交
    • J
      drm/i915: Refer to GGTT {,VM} consistently · 72e96d64
      Joonas Lahtinen 提交于
      Refer to the GGTT VM consistently as "ggtt->base" instead of just "ggtt",
      "vm" or indirectly through other variables like "dev_priv->ggtt.base"
      to avoid confusion with the i915_ggtt object itself and PPGTT VMs.
      
      Refer to the GGTT as "ggtt" instead of indirectly through chaining.
      
      As a bonus gets rid of the long-standing i915_obj_to_ggtt vs.
      i915_gem_obj_to_ggtt conflict, due to removal of i915_obj_to_ggtt!
      
      v2:
      - Added some more after grepping sources with Chris
      
      v3:
      - Refer to GGTT VM through ggtt->base consistently instead of ggtt_vm
        (Chris)
      
      v4:
      - Convert all dev_priv->ggtt->foo accesses to ggtt->foo.
      
      v5:
      - Make patch checker happy
      
      Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
      Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
      Cc: Chris Wilson <chris@chris-wilson.co.uk>
      Signed-off-by: NJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
      Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
      72e96d64
  25. 18 3月, 2016 1 次提交
  26. 26 2月, 2016 1 次提交
  27. 16 2月, 2016 1 次提交
  28. 06 2月, 2016 1 次提交
    • S
      drm/i915/bxt: Check BIOS RC6 setup before enabling RC6 · 274008e8
      Sagar Arun Kamble 提交于
      RC6 setup is shared between BIOS and Driver. BIOS sets up subset of RC6
      setup registers. If those are not setup Driver should not enable RC6.
      For implementing this, driver can check RC_CTRL0 and RC_CTRL1 values
      to know if BIOS has enabled HW/SW RC6.
      This will also enable user to control RC6 using BIOS settings alone.
      RC6 related instability can be avoided by disabling via BIOS settings
      till driver fixes it.
      
      v2: Had placed logic in gen8 function by mistake. Fixed it.
      Ensuring RPM is not enabled in case BIOS disabled RC6.
      
      v3: Need to disable RPM if RC6 is disabled due to BIOS settings. (Daniel)
      Runtime PM enabling happens before gen9_enable_rc6.
      Moved the updation of enable_rc6 parameter in intel_uncore_sanitize.
      
      v4: Added elaborate check for BIOS RC6 setup. Prepared check_pctx for bxt.
          (Imre)
      
      v5: Caching reserved stolen base and size in the driver private data.
          Reorganized RC6 setup check. Moved from gen9_enable_rc6 to
          intel_uncore_sanitize. (Imre)
      
      v6: Rebasing on the patch submitted by Imre that moves gem_init_stolen
          earlier in the load.
      
      v7: Removed PWRCTX_MAXCNT_VCSUNIT1 check as it applies to SKL. (Imre)
      
      v8: Fixed formatting and checkpatch issues. Fixed functional issue where
          RC6 ctx size check was missing. (Imre)
      
      Cc: Imre Deak <imre.deak@intel.com>
      Signed-off-by: NSagar Arun Kamble <sagar.a.kamble@intel.com>
      Signed-off-by: NImre Deak <imre.deak@intel.com>
      Link: http://patchwork.freedesktop.org/patch/msgid/1454697809-22113-1-git-send-email-sagar.a.kamble@intel.com
      274008e8
  29. 06 1月, 2016 1 次提交
  30. 22 12月, 2015 1 次提交
  31. 17 12月, 2015 1 次提交
  32. 29 10月, 2015 1 次提交
    • R
      drm/i915/kbl: Introduce Kabylake platform defition. · ef11bdb3
      Rodrigo Vivi 提交于
      Kabylake is a Intel® Processor containing Intel® HD Graphics
      following Skylake.
      
      It is Gen9p5, so it inherits everything from Skylake.
      
      Let's start by adding the platform separated from Skylake
      but reusing most of all features, functions etc. Later we
      rebase the PCI-ID patch without is_skylake=1
      so we don't replace what original Author did there.
      
      Few IS_SKYLAKEs if statements are not being covered by this patch
      on purpose:
         - Workarounds: Kabylake is derivated from Skylake H0 so no
           		  W/As apply here.
         - GuC: A following patch removes Kabylake support with an
           	  explanation: No firmware available yet.
         - DMC/CSR: Done in a separated patch since we need to be carefull
           	      and load the version for revision 7 since
      	      Kabylake is Skylake H0.
      
      v2: relative cleaner commit message and added the missed
          IS_KABYLAKE to intel_i2c.c as pointed out by Jani.
      
      Cc: Jani Nikula <jani.nikula@intel.com>
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      Signed-off-by: NJani Nikula <jani.nikula@intel.com>
      ef11bdb3