1. 13 8月, 2007 1 次提交
  2. 22 7月, 2007 2 次提交
  3. 18 7月, 2007 1 次提交
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      Freezer: make kernel threads nonfreezable by default · 83144186
      Rafael J. Wysocki 提交于
      Currently, the freezer treats all tasks as freezable, except for the kernel
      threads that explicitly set the PF_NOFREEZE flag for themselves.  This
      approach is problematic, since it requires every kernel thread to either
      set PF_NOFREEZE explicitly, or call try_to_freeze(), even if it doesn't
      care for the freezing of tasks at all.
      
      It seems better to only require the kernel threads that want to or need to
      be frozen to use some freezer-related code and to remove any
      freezer-related code from the other (nonfreezable) kernel threads, which is
      done in this patch.
      
      The patch causes all kernel threads to be nonfreezable by default (ie.  to
      have PF_NOFREEZE set by default) and introduces the set_freezable()
      function that should be called by the freezable kernel threads in order to
      unset PF_NOFREEZE.  It also makes all of the currently freezable kernel
      threads call set_freezable(), so it shouldn't cause any (intentional)
      change of behaviour to appear.  Additionally, it updates documentation to
      describe the freezing of tasks more accurately.
      
      [akpm@linux-foundation.org: build fixes]
      Signed-off-by: NRafael J. Wysocki <rjw@sisk.pl>
      Acked-by: NNigel Cunningham <nigel@nigel.suspend2.net>
      Cc: Pavel Machek <pavel@ucw.cz>
      Cc: Oleg Nesterov <oleg@tv-sign.ru>
      Cc: Gautham R Shenoy <ego@in.ibm.com>
      Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      83144186
  4. 09 5月, 2007 1 次提交
  5. 03 5月, 2007 3 次提交
  6. 09 4月, 2007 1 次提交
  7. 01 3月, 2007 1 次提交
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      [PATCH] x86_64/i386 irq: Fix !CONFIG_SMP compilation · 2ff7354f
      Eric W. Biederman 提交于
      When removing set_native_irq I missed the fact that it was
      called in a couple of places that were compiled even when
      SMP support is disabled.  And since the irq_desc[].affinity
      field only exists in SMP things broke.
      
      Thanks to Simon Arlott <simon@arlott.org> for spotting this.
      
      There are a couple of ways to fix this but the simplest one
      is to just remove the assignments.  The affinity field is only
      used to display a value to the user, and nothing on either i386
      or x86_64 reads it or depends on it being any particlua value,
      so skipping the assignment is safe.  The assignment that
      is being removed is just for the initial affinity value before
      the user explicitly sets it.  The irq_desc array initializes
      this field to CPU_MASK_ALL so the field is initialized to
      a reasonable value in the SMP case without being set.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      2ff7354f
  8. 27 2月, 2007 1 次提交
  9. 17 2月, 2007 3 次提交
  10. 13 2月, 2007 2 次提交
  11. 10 2月, 2007 1 次提交
  12. 08 2月, 2007 1 次提交
  13. 31 1月, 2007 1 次提交
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      [PATCH] i386: In assign_irq_vector look at all vectors before giving up · 8339f000
      Eric W. Biederman 提交于
      When the world was a simple and static place setting up irqs was easy.
      It sufficed to allocate a linux irq number and a find a free cpu
      vector we could receive that linux irq on.  In those days it was
      a safe assumption that any allocated vector was actually in use
      so after one global pass through all of the vectors we would have
      none left.
      
      These days things are much more dynamic with interrupt controllers
      (in the form of MSI or MSI-X) appearing on plug in cards and linux
      irqs appearing and disappearing.  As these irqs come and go vectors
      are allocated and freed,  invalidating the ancient assumption that all
      allocated vectors stayed in use forever.
      
      So this patch modifies the vector allocator to walk through every
      possible vector before giving up, and to check to see if a vector
      is in use before assigning it.  With these changes we stop leaking
      freed vectors and it becomes possible to allocate and free irq vectors
      all day long.
      
      This changed was modeled after the vector allocator on x86_64 where
      this limitation has already been removed.  In essence we don't update
      the static variables that hold the position of the last vector we
      allocated until have successfully allocated another vector.  This
      allows us to detect if we have completed one complete scan through
      all of the possible vectors.
      Acked-by: NAuke Kok <auke-jan.h.kok@intel.com>
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      8339f000
  14. 10 12月, 2006 1 次提交
    • A
      [PATCH] i386: Fix io_apic.c warning · 306a22c2
      Andi Kleen 提交于
      gcc 4.2 warns
      
      linux/arch/i386/kernel/io_apic.c: In function ‘create_irq’:
      linux/arch/i386/kernel/io_apic.c:2488: warning: ‘vector’ may be used uninitialized in this function
      
      The warning is false, but somewhat legitimate so work around it.
      Signed-off-by: NAndi Kleen <ak@suse.de>
      306a22c2
  15. 08 12月, 2006 1 次提交
  16. 07 12月, 2006 5 次提交
  17. 16 11月, 2006 1 次提交
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      [PATCH] Use delayed disable mode of ioapic edge triggered interrupts · 45c99533
      Eric W. Biederman 提交于
      Komuro reports that ISA interrupts do not work after a disable_irq(),
      causing some PCMCIA drivers to not work, with messages like
      
      	eth0: Asix AX88190: io 0x300, irq 3, hw_addr xx:xx:xx:xx:xx:xx
      	eth0: found link beat
      	eth0: autonegotiation complete: 100baseT-FD selected
      	eth0: interrupt(s) dropped!
      	eth0: interrupt(s) dropped!
      	eth0: interrupt(s) dropped!
      	...
      
      Linus Torvalds <torvalds@osdl.org> said:
      
        "Now, edge-triggered interrupts are a _lot_ harder to mask, because the
         Intel APIC is an unbelievable piece of sh*t, and has the edge-detect logic
         _before_ the mask logic, so if a edge happens _while_ the device is
         masked, you'll never ever see the edge ever again (unmasking will not
         cause a new edge, so you simply lost the interrupt).
      
         So when you "mask" an edge-triggered IRQ, you can't really mask it at all,
         because if you did that, you'd lose it forever if the IRQ comes in while
         you masked it. Instead, we're supposed to leave it active, and set a flag,
         and IF the IRQ comes in, we just remember it, and mask it at that point
         instead, and then on unmasking, we have to replay it by sending a
         self-IPI."
      
      This trivial patch solves the problem.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@redhat.com>
      Acked-by: NKomuro <komurojun-mbn@nifty.com>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      45c99533
  18. 09 11月, 2006 1 次提交
  19. 02 11月, 2006 2 次提交
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      i386: write IO APIC irq routing entries in correct order · f9dadfa7
      Linus Torvalds 提交于
      Since the "mask" bit is in the low word, when we write a new entry, we
      need to write the high word first, before we potentially unmask it.
      
      The exception is when we actually want to mask the interrupt, in which
      case we want to write the low word first to make sure that the high word
      doesn't change while the interrupt routing is still active.
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f9dadfa7
    • L
      i386: clean up io-apic accesses · 130fe05d
      Linus Torvalds 提交于
      This is preparation for fixing the ordering of the accesses that
      got broken by the commit cf4c6a2f when
      factoring out the "common" io apic routing entry accesses.
      
      Move the accessor function (that were only used by io_apic.c) out
      of a header file, and use proper memory-mapped accesses rather than
      making up our own "volatile" pointers.
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      130fe05d
  20. 17 10月, 2006 1 次提交
  21. 12 10月, 2006 1 次提交
  22. 09 10月, 2006 1 次提交
  23. 04 10月, 2006 7 次提交
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      [PATCH] htirq: tidy up the htirq code · 95d77884
      Eric W. Biederman 提交于
      This moves the declarations for the architecture helpers into
      include/linux/htirq.h from the generic include/linux/pci.h.  Hopefully this
      will make this distinction clearer.
      
      htirq.h is included where it is needed.
      
      The dependency on the msi code is fixed and removed.
      
      The Makefile is tidied up.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      95d77884
    • E
      [PATCH] msi: refactor and move the msi irq_chip into the arch code · 3b7d1921
      Eric W. Biederman 提交于
      It turns out msi_ops was simply not enough to abstract the architecture
      specific details of msi.  So I have moved the resposibility of constructing
      the struct irq_chip to the architectures, and have two architecture specific
      functions arch_setup_msi_irq, and arch_teardown_msi_irq.
      
      For simple architectures those functions can do all of the work.  For
      architectures with platform dependencies they can call into the appropriate
      platform code.
      
      With this msi.c is finally free of assuming you have an apic, and this
      actually takes less code.
      
      The helpers for the architecture specific code are declared in the linux/msi.h
      to keep them separate from the msi functions used by drivers in linux/pci.h
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Tony Luck <tony.luck@intel.com>
      Cc: Andi Kleen <ak@suse.de>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Greg KH <greg@kroah.com>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      3b7d1921
    • E
      [PATCH] Initial generic hypertransport interrupt support · 8b955b0d
      Eric W. Biederman 提交于
      This patch implements two functions ht_create_irq and ht_destroy_irq for
      use by drivers.  Several other functions are implemented as helpers for
      arch specific irq_chip handlers.
      
      The driver for the card I tested this on isn't yet ready to be merged.
      However this code is and hypertransport irqs are in use in a few other
      places in the kernel.  Not that any of this will get merged before 2.6.19
      
      Because the ipath-ht400 is slightly out of spec this code will need to be
      generalized to work there.
      
      I think all of the powerpc uses are for a plain interrupt controller in a
      chipset so support for native hypertransport devices is a little less
      interesting.
      
      However I think this is a half way decent model on how to separate arch
      specific and generic helper code, and I think this is a functional model of
      how to get the architecture dependencies out of the msi code.
      
      [akpm@osdl.org: Kconfig fix]
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Greg KH <greg@kroah.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      8b955b0d
    • E
      [PATCH] genirq: i386 irq: Remove the msi assumption that irq == vector · ace80ab7
      Eric W. Biederman 提交于
      This patch removes the change in behavior of the irq allocation code when
      CONFIG_PCI_MSI is defined.  Removing all instances of the assumption that irq
      == vector.
      
      create_irq is rewritten to first allocate a free irq and then to assign that
      irq a vector.
      
      assign_irq_vector is made static and the AUTO_ASSIGN case which allocates an
      vector not bound to an irq is removed.
      
      The ioapic vector methods are removed, and everything now works with irqs.
      
      The definition of NR_IRQS no longer depends on CONFIG_PCI_MSI
      
      [akpm@osdl.org: cleanup]
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      ace80ab7
    • E
      [PATCH] genirq: i386 irq: Move msi message composition into io_apic.c · 2d3fcc1c
      Eric W. Biederman 提交于
      This removes the hardcoded assumption that irq == vector in the msi
      composition code, and it allows the msi message composition to setup logical
      mode, or lowest priorirty delivery mode as we do for other apic interrupts,
      and with the same selection criteria.
      
      Basically this moves the problem of what is in the msi message into the
      architecture irq management code where it belongs.  Not in a generic layer
      that doesn't have enough information to compose msi messages properly.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      2d3fcc1c
    • E
      [PATCH] genirq: i386 irq: Dynamic irq support · 3fc471ed
      Eric W. Biederman 提交于
      The current implementation of create_irq() is a hack but it is the current
      hack that msi.c uses, and unfortunately the ``generic'' apic msi ops depend on
      this hack.  Thus we are stuck this hack of assuming irq == vector until the
      depencencies in the generic msi code are removed.
      Signed-off-by: NEric W. Biederman <ebiederm@xmission.com>
      Cc: Ingo Molnar <mingo@elte.hu>
      Cc: Thomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Rajesh Shah <rajesh.shah@intel.com>
      Cc: Andi Kleen <ak@muc.de>
      Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com>
      Cc: "Luck, Tony" <tony.luck@intel.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      3fc471ed
    • I
      [PATCH] genirq: convert the i386 architecture to irq-chips · f5b9ed7a
      Ingo Molnar 提交于
      This patch converts all the i386 PIC controllers (except VisWS and Voyager,
      which I could not test - but which should still work as old-style IRQ layers)
      to the new and simpler irq-chip interrupt handling layer.
      
      [akpm@osdl.org: build fix]
      [mingo@elte.hu: enable fasteoi handler for i386 level-triggered IO-APIC irqs]
      Signed-off-by: NIngo Molnar <mingo@elte.hu>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
      Cc: Roland Dreier <rolandd@cisco.com>
      Signed-off-by: NAndrew Morton <akpm@osdl.org>
      Signed-off-by: NLinus Torvalds <torvalds@osdl.org>
      f5b9ed7a