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  1. 29 7月, 2011 1 次提交
  3. 28 7月, 2011 8 次提交
    • G
      arm/dt: tegra devicetree support · 8e267f3d
      由 Grant Likely 提交于 
      Everything required to populate NVIDIA Tegra devices from the device
tree.  This patch adds a new DT_MACHINE_DESC() which matches against
a tegra20 device tree.  So far it only registers the on-chip devices,
but it will be refined in follow on patches to configure clocks and
pin IO from the device tree also.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      8e267f3d
    • G
      arm/versatile: Add device tree support · 3ba7222a
      由 Grant Likely 提交于 
      For testing the dt work, define a dt-enabled versatile platform.

This patch adds a new versatile platform for when using the device
tree.  Add platform and amba devices are discovered and registered by
parsing the device tree.  Clocks and initial io mappings are still
configured statically.

This patch still depends on some static platform_data for a few devices
which is passed via the auxdata structure to of_platform_populate(),
but it is a viable starting point until the drivers can get all
configuration data out of the device tree.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      3ba7222a
    • G
      irq: add irq_domain translation infrastructure · 08a543ad
      由 Grant Likely 提交于 
      This patch adds irq_domain infrastructure for translating from
hardware irq numbers to linux irqs.  This is particularly important
for architectures adding device tree support because the current
implementation (excluding PowerPC and SPARC) cannot handle
translation for more than a single interrupt controller.  irq_domain
supports device tree translation for any number of interrupt
controllers.

This patch converts x86, Microblaze, ARM and MIPS to use irq_domain
for device tree irq translation.  x86 is untested beyond compiling it,
irq_domain is enabled for MIPS and Microblaze, but the old behaviour is
preserved until the core code is modified to actually register an
irq_domain yet.  On ARM it works and is required for much of the new
ARM device tree board support.

PowerPC has /not/ been converted to use this new infrastructure.  It
is still missing some features before it can replace the virq
infrastructure already in powerpc (see documentation on
irq_domain_map/unmap for details).  Followup patches will add the
missing pieces and migrate PowerPC to use irq_domain.

SPARC has its own method of managing interrupts from the device tree
and is unaffected by this change.
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
      08a543ad
    • D
      sparc: Detect and handle UltraSPARC-T3 cpu types. · 4ba991d3
      由 David S. Miller 提交于 
      The cpu compatible string we look for is "SPARC-T3".

As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+.  Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.

We use the Niagara-T2 perf support, since T3 is a close relative in
this regard.  Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.

For now I haven't added any new ELF hwcap flags.  We probably need
to add a couple, for example:

T2 and T3 both support the population count instruction in hardware.

T3 supports VIS3 instructions, including support (finally) for
partitioned shift.  One can also now move directly between float
and integer registers.

T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply.  Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.

T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.

So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      4ba991d3
    • D
      sparc: Don't do expensive hypervisor PCR write unless necessary. · 314ff527
      由 David S. Miller 提交于 
      The hypervisor call is only necessary if hypervisor events are
being requested.

So if we're not tracking hypervisor events, simply do a direct
register write.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      314ff527
    • D
      sparc: Add T3 sun4v cpu type and hypervisor group defines. · 15e3608d
      由 David S. Miller 提交于 
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      15e3608d
    • D
      sparc: Don't leave sparc_pmu_type NULL on sun4v. · facfddef
      由 David S. Miller 提交于 
      Otherwise we'll crash in the sparc perf init code.
Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      facfddef
    • S
      sparc: rename atomic_add_unless · 678624e4
      由 Stephen Rothwell 提交于 
      Should have been done in commit 1af08a1407f4 ("This is in preparation
for more generic atomic").
Signed-off-by: NStephen Rothwell <sfr@canb.auug.org.au>
Cc: Arun Sharma <asharma@fb.com>
Cc: David Miller <davem@davemloft.net>
Cc: "Hans-Christian Egtvedt" <hans-christian.egtvedt@atmel.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
      678624e4
  5. 27 7月, 2011 16 次提交
  7. 26 7月, 2011 15 次提交