1. 01 2月, 2015 1 次提交
  2. 22 1月, 2015 2 次提交
  3. 29 12月, 2014 2 次提交
  4. 01 12月, 2014 1 次提交
  5. 24 11月, 2014 2 次提交
  6. 04 9月, 2014 2 次提交
  7. 25 6月, 2014 1 次提交
  8. 16 5月, 2014 1 次提交
  9. 13 4月, 2014 1 次提交
  10. 10 3月, 2014 1 次提交
    • A
      iwlwifi: pcie: enable LP XTAL to reduce power consumption · a812cba9
      Alexander Bondar 提交于
      1. Enable LP XTAL to avoid HW bug where device may consume much
      power if FW is not loaded after device reset. LP XTAL is
      disabled by default after device HW reset. Configure device's
      "persistence" mode to avoid resetting XTAL again when SHRD_HW_RST
      occurs in S3.
      
      2. Add methods to access SHR (shared block memory space) directly from PCI
      bus w/o need to power up MAC HW.
      
      Shared internal registers (e.g. SHR_APMG_GP1, SHR_APMG_XTAL_CFG)can be
      accessed directly from PCI bus through SHR arbiter even when MAC HW is
      powered down. This is possible due to indirect read/write via
      HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and HEEP_CTRL_WRD_PCIEX_DATA (0xF4)
      registers.
      
      Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
      need not be powered up so no "grab inc access" is required.
      
      For example, to read from SHR_APMG_GP1 register (0x1DC),
      first, write to the control register:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
      second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
      
      To write the register, first, write to the data register
      HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
      HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
      HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
      Signed-off-by: NAlexander Bondar <alexander.bondar@intel.com>
      Signed-off-by: NEmmanuel Grumbach <emmanuel.grumbach@intel.com>
      a812cba9
  11. 04 2月, 2014 2 次提交
  12. 14 1月, 2014 1 次提交
  13. 01 1月, 2014 1 次提交
  14. 10 12月, 2013 1 次提交
  15. 03 10月, 2013 1 次提交
  16. 06 8月, 2013 1 次提交
  17. 26 7月, 2013 1 次提交
  18. 29 5月, 2013 1 次提交
  19. 06 3月, 2013 1 次提交
  20. 31 1月, 2013 1 次提交
  21. 24 1月, 2013 1 次提交
  22. 16 10月, 2012 1 次提交
  23. 09 6月, 2012 1 次提交
  24. 06 6月, 2012 1 次提交
  25. 25 4月, 2012 1 次提交
    • J
      iwlwifi: fix hardware queue programming · 5ef4acd5
      Johannes Berg 提交于
      Newer devices have 20 (5000 series) or 30 (6000 series)
      hardware queues, rather than the 16 that 4965 had. This
      was added to the driver a long time ago, but improperly:
      the queue registers for the higher queues aren't just
      continuations of the registers for the first 16 queues,
      they are in other places. Therefore, the hardware would
      lock up when trying to activate queue 16 or above and
      the device would have to be restarted.
      
      Thanks goes to Emmanuel who identified this and told me
      how the queue programming should be done.
      
      Note that we don't use queues 20 and higher today and
      doing so needs more work than this.
      
      Cc: stable@vger.kernel.org
      Signed-off-by: NJohannes Berg <johannes.berg@intel.com>
      Signed-off-by: NWey-Yi Guy <wey-yi.w.guy@intel.com>
      Signed-off-by: NJohn W. Linville <linville@tuxdriver.com>
      5ef4acd5
  26. 10 3月, 2012 1 次提交
  27. 25 1月, 2012 1 次提交
  28. 07 1月, 2012 1 次提交
  29. 30 8月, 2011 2 次提交
  30. 16 7月, 2011 1 次提交
  31. 01 7月, 2011 1 次提交
  32. 08 4月, 2011 3 次提交