1. 22 4月, 2008 1 次提交
  2. 05 4月, 2008 1 次提交
  3. 03 2月, 2008 1 次提交
  4. 12 1月, 2008 1 次提交
  5. 26 11月, 2007 1 次提交
    • A
      [MTD] [NOR] Prevent erase command invocation on suspended chip · 6c24e416
      Alexander Belyakov 提交于
      while running stress tests we have met cfi_cmdset_0001.c driver issue.
      Working on multipartitional devices with erase suspend on write
      feature enabled it is possible to get erase operation invoked on chip
      with suspended erase. get_chip() looses information about earlier
      suspended erase and new erase operation gets issued. New erase
      operations report successful completion, but blocks remain dirty
      causing, for example, JFFS2 error messages like:
      
      ...
      Newly-erased block contained word 0x20031985 at offset 0x00200000
      Newly-erased block contained word 0x20031985 at offset 0x00280000
      Newly-erased block contained word 0x20031985 at offset 0x00240000
      ...
      
      The patch below fixes that issue.
      Signed-off-by: NAlexander Belyakov <alexander.belyakov@intel.com>
      Acked-by: NNicolas Pitre <nico@cam.org>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      6c24e416
  6. 23 11月, 2007 1 次提交
  7. 31 10月, 2007 1 次提交
  8. 23 10月, 2007 1 次提交
  9. 13 10月, 2007 1 次提交
  10. 24 9月, 2007 1 次提交
  11. 05 7月, 2007 1 次提交
  12. 29 6月, 2007 2 次提交
  13. 03 4月, 2007 1 次提交
  14. 09 2月, 2007 2 次提交
  15. 29 11月, 2006 2 次提交
  16. 21 10月, 2006 1 次提交
  17. 15 7月, 2006 1 次提交
    • A
      [MTD] Fixes of performance and stability issues in CFI driver. · 46a1652c
      Alexey Korolev 提交于
      Fix of performance and stability issues on Intel NOR chips. It fixes:
      
      1. Very low write performance on Sibley (perf tests demonstrated write
         performance less than 100Kb/sec when it should be over 400Kb/sec).
      
      2. Low erase performance. (perf tests on Sibleuy demonstrated erase
         performance 246Kb/sec when it should be over 300Kb/sec).
      
      3. Error on JFFS2 tests with CPU loading application when MTD returns
         "block erase error: (status timeout)" To fix the issue it does the
         following:
           1. Removes the timeout tuning from inval_cache_and_wait_for_operation.
           2. Waiting conditions in inval_cache_and_wait_for_operation now is
               based on timer resolution
              If timeout is lower than timer resolution then we do in cycle
      	  "Checking the status"
      	  udelay(1);
      	  cond_resched();
              If timeout is greater than timer resolution (probably erase
              operation) We do the following
      	  sleep for half of operation timeout and do in cycle the following
      	    "Checking the status"
      	    sleep for timer resolution
      Signed-off-by: NNicolas Pitre <nico@cam.org>
      Signed-off-by: NAlexey Korolev <akorolev@infradead.org>
      Signed-off-by: NDavid Woodhouse <dwmw2@infradead.org>
      46a1652c
  18. 22 6月, 2006 1 次提交
  19. 23 5月, 2006 2 次提交
    • J
      [MTD] Introduce MTD_BIT_WRITEABLE · 5fa43394
      Joern Engel 提交于
      o Add a flag MTD_BIT_WRITEABLE for devices that allow single bits to be
        cleared.
      o Replace MTD_PROGRAM_REGIONS with a cleared MTD_BIT_WRITEABLE flag for
        STMicro and Intel Sibley flashes with internal ECC.  Those flashes
        disallow clearing of single bits, unlike regular NOR flashes, so the
        new flag models their behaviour better.
      o Remove MTD_ECC.  After the STMicro/Sibley merge, this flag is only set
        and never checked.
      Signed-off-by: NJoern Engel <joern@wh.fh-wedel.de>
      5fa43394
    • J
      [MTD] Introduce writesize · 28318776
      Joern Engel 提交于
      At least two flashes exists that have the concept of a minimum write unit,
      similar to NAND pages, but no other NAND characteristics.  Therefore, rename
      the minimum write unit to "writesize" for all flashes, including NAND.
      Signed-off-by: NJoern Engel <joern@wh.fh-wedel.de>
      28318776
  20. 17 5月, 2006 3 次提交
  21. 14 5月, 2006 1 次提交
  22. 09 5月, 2006 1 次提交
  23. 25 2月, 2006 1 次提交
  24. 21 2月, 2006 1 次提交
  25. 30 11月, 2005 1 次提交
  26. 07 11月, 2005 6 次提交
  27. 04 8月, 2005 1 次提交
    • T
      [MTD] CHIPS: Recognize Spansion CFI 1.4 chips · d88f977b
      Todd Poynor 提交于
      Modify Amd/Fujitsu CFI NOR flash primary vendor extension table revision
      check to recognize version 1.4.  Verified the existing driver can
      handle version 1.4 chips without additional info from 1.4 extended table.
      
      Move the primary vendor extension table revision check from common file
      to the 3 CFI chip driver files, since the data structures and revisions
      handled by those data structures are specific to the chip driver.
      
      Modify the error message printed when the revision is unknown to be a
      KERN_ERR instead of WARNING since this will cause mtd to ignore the chip.
      Signed-off-by: NTodd Poynor <tpoynor@mvista.com>
      Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
      d88f977b
  28. 07 7月, 2005 1 次提交
  29. 23 5月, 2005 1 次提交