1. 17 4月, 2013 5 次提交
    • W
      ARM: 7698/1: perf: fix group validation when using enable_on_exec · cb2d8b34
      Will Deacon 提交于
      Events may be created with attr->disabled == 1 and attr->enable_on_exec
      == 1, which confuses the group validation code because events with the
      PERF_EVENT_STATE_OFF are not considered candidates for scheduling, which
      may lead to failure at group scheduling time.
      
      This patch fixes the validation check for ARM, so that events in the
      OFF state are still considered when enable_on_exec is true.
      
      Cc: stable@vger.kernel.org
      Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
      Cc: Arnaldo Carvalho de Melo <acme@ghostprotocols.net>
      Cc: Jiri Olsa <jolsa@redhat.com>
      Reported-by: NSudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      cb2d8b34
    • B
      ARM: 7697/1: hw_breakpoint: do not use __cpuinitdata for dbg_cpu_pm_nb · 50acff3c
      Bastian Hecht 提交于
      We must not declare dbg_cpu_pm_nb as __cpuinitdata as we need it after
      system initialization for Suspend and CPUIdle.
      
      This was done in commit 9a6eb310 ("ARM: hw_breakpoint: Debug powerdown
      support for self-hosted debug").
      
      Cc: stable@vger.kernel.org
      Cc: Dietmar Eggemann <Dietmar.Eggemann@arm.com>
      Signed-off-by: NBastian Hecht <hechtb+renesas@gmail.com>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      50acff3c
    • I
      ARM: 7696/1: Fix kexec by setting outer_cache.inv_all for Feroceon · cd272d1e
      Illia Ragozin 提交于
      On Feroceon the L2 cache becomes non-coherent with the CPU
      when the L1 caches are disabled. Thus the L2 needs to be invalidated
      after both L1 caches are disabled.
      
      On kexec before the starting the code for relocation the kernel,
      the L1 caches are disabled in cpu_froc_fin (cpu_v7_proc_fin for Feroceon),
      but after L2 cache is never invalidated, because inv_all is not set
      in cache-feroceon-l2.c.
      So kernel relocation and decompression may has (and usually has) errors.
      Setting the function enables L2 invalidation and fixes the issue.
      
      Cc: <stable@vger.kernel.org>
      Signed-off-by: NIllia Ragozin <illia.ragozin@grapecom.com>
      Acked-by: NJason Cooper <jason@lakedaemon.net>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      cd272d1e
    • J
      ARM: 7694/1: ARM, TCM: initialize TCM in paging_init(), instead of setup_arch() · de40614e
      Joonsoo Kim 提交于
      tcm_init() call iotable_init() and it use early_alloc variants which
      do memblock allocation. Directly using memblock allocation after
      initializing bootmem should not permitted, because bootmem can't know
      where are additinally reserved.
      So move tcm_init() to a safe place before initalizing bootmem.
      
      (On the U300)
      Tested-by: NLinus Walleij <linus.walleij@linaro.org>
      Signed-off-by: NJoonsoo Kim <iamjoonsoo.kim@lge.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      de40614e
    • A
      ARM: 7692/1: iop3xx: move IOP3XX_PERIPHERAL_VIRT_BASE · f5d6a144
      Aaro Koskinen 提交于
      Currently IOP3XX_PERIPHERAL_VIRT_BASE conflicts with PCI_IO_VIRT_BASE:
      
      					address         size
      	PCI_IO_VIRT_BASE                0xfee00000      0x200000
      	IOP3XX_PERIPHERAL_VIRT_BASE     0xfeffe000      0x2000
      
      Fix by moving IOP3XX_PERIPHERAL_VIRT_BASE below PCI_IO_VIRT_BASE.
      
      The patch fixes the following kernel panic with 3.9-rc1 on iop3xx boards:
      
      [    0.000000] Booting Linux on physical CPU 0x0
      [    0.000000] Initializing cgroup subsys cpu
      [    0.000000] Linux version 3.9.0-rc1-iop32x (aaro@blackmetal) (gcc version 4.7.2 (GCC) ) #20 PREEMPT Tue Mar 5 16:44:36 EET 2013
      [    0.000000] bootconsole [earlycon0] enabled
      [    0.000000] ------------[ cut here ]------------
      [    0.000000] kernel BUG at mm/vmalloc.c:1145!
      [    0.000000] Internal error: Oops - BUG: 0 [#1] PREEMPT ARM
      [    0.000000] Modules linked in:
      [    0.000000] CPU: 0    Not tainted  (3.9.0-rc1-iop32x #20)
      [    0.000000] PC is at vm_area_add_early+0x4c/0x88
      [    0.000000] LR is at add_static_vm_early+0x14/0x68
      [    0.000000] pc : [<c03e74a8>]    lr : [<c03e1c40>]    psr: 800000d3
      [    0.000000] sp : c03ffee4  ip : dfffdf88  fp : c03ffef4
      [    0.000000] r10: 00000002  r9 : 000000cf  r8 : 00000653
      [    0.000000] r7 : c040eca8  r6 : c03e2408  r5 : dfffdf60  r4 : 00200000
      [    0.000000] r3 : dfffdfd8  r2 : feffe000  r1 : ff000000  r0 : dfffdf60
      [    0.000000] Flags: Nzcv  IRQs off  FIQs off  Mode SVC_32  ISA ARM  Segment kernel
      [    0.000000] Control: 0000397f  Table: a0004000  DAC: 00000017
      [    0.000000] Process swapper (pid: 0, stack limit = 0xc03fe1b8)
      [    0.000000] Stack: (0xc03ffee4 to 0xc0400000)
      [    0.000000] fee0:          00200000 c03fff0c c03ffef8 c03e1c40 c03e7468 00200000 fee00000
      [    0.000000] ff00: c03fff2c c03fff10 c03e23e4 c03e1c38 feffe000 c0408ee4 ff000000 c0408f04
      [    0.000000] ff20: c03fff3c c03fff30 c03e2434 c03e23b4 c03fff84 c03fff40 c03e2c94 c03e2414
      [    0.000000] ff40: c03f8878 c03f6410 ffff0000 000bffff 00001000 00000008 c03fff84 c03f6410
      [    0.000000] ff60: c04227e8 c03fffd4 a0008000 c03f8878 69052e30 c02f96eb c03fffbc c03fff88
      [    0.000000] ff80: c03e044c c03e268c 00000000 0000397f c0385130 00000001 ffffffff c03f8874
      [    0.000000] ffa0: dfffffff a0004000 69052e30 a03f61a0 c03ffff4 c03fffc0 c03dd5cc c03e0184
      [    0.000000] ffc0: 00000000 00000000 00000000 00000000 00000000 c03f8878 0000397d c040601c
      [    0.000000] ffe0: c03f8874 c0408674 00000000 c03ffff8 a0008040 c03dd558 00000000 00000000
      [    0.000000] Backtrace:
      [    0.000000] [<c03e745c>] (vm_area_add_early+0x0/0x88) from [<c03e1c40>] (add_static_vm_early+0x14/0x68)
      Tested-by: NMikael Pettersson <mikpe@it.uu.se>
      Signed-off-by: NAaro Koskinen <aaro.koskinen@iki.fi>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      f5d6a144
  2. 08 4月, 2013 5 次提交
  3. 07 4月, 2013 1 次提交
  4. 06 4月, 2013 1 次提交
    • J
      x86: Fix rebuild with EFI_STUB enabled · 91870824
      Jan Beulich 提交于
      eboot.o and efi_stub_$(BITS).o didn't get added to "targets", and hence
      their .cmd files don't get included by the build machinery, leading to
      the files always getting rebuilt.
      
      Rather than adding the two files individually, take the opportunity and
      add $(VMLINUX_OBJS) to "targets" instead, thus allowing the assignment
      at the top of the file to be shrunk quite a bit.
      
      At the same time, remove a pointless flags override line - the variable
      assigned to was misspelled anyway, and the options added are
      meaningless for assembly sources.
      
      [ hpa: the patch is not minimal, but I am taking it for -urgent anyway
        since the excess impact of the patch seems to be small enough. ]
      Signed-off-by: NJan Beulich <jbeulich@suse.com>
      Link: http://lkml.kernel.org/r/515C5D2502000078000CA6AD@nat28.tlf.novell.com
      Cc: Matthew Garrett <mjg@redhat.com>
      Cc: Matt Fleming <matt.fleming@intel.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      91870824
  5. 05 4月, 2013 6 次提交
  6. 03 4月, 2013 7 次提交
    • P
      ARM: 7690/1: mm: fix CONFIG_LPAE typos · 4e1db26a
      Paul Bolle 提交于
      CONFIG_LPAE doesn't exist: the correct option is CONFIG_ARM_LPAE, so fix
      up the two typos under arch/arm/.
      
      The fix to head.S is slightly scary, but this is just for setting up
      an early io-mapping for the serial port when running on a big-endian,
      LPAE system. Since these systems don't exist in the wild (at least, I
      have no access to one outside of kvmtool, which doesn't provide a serial
      port suitable for earlyprintk), then we can revisit the code later if it
      causes any problems.
      Signed-off-by: NPaul Bolle <pebolle@tiscali.nl>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      4e1db26a
    • R
      ARM: 7689/1: add unwind annotations to ftrace asm · b21e023b
      Rabin Vincent 提交于
      Add unwind annotations to the ftrace assembly code so that the function
      tracer's stacktracing options (func_stack_trace, etc.) work when
      CONFIG_ARM_UNWIND is enabled.
      Signed-off-by: NRabin Vincent <rabin@rab.in>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      b21e023b
    • W
      ARM: 7685/1: delay: use private ticks_per_jiffy field for timer-based delay ops · 6f3d90e5
      Will Deacon 提交于
      Commit 70264367 ("ARM: 7653/2: do not scale loops_per_jiffy when
      using a constant delay clock") fixed a problem with our timer-based
      delay loop, where loops_per_jiffy is scaled by cpufreq yet used directly
      by the timer delay ops.
      
      This patch fixes the problem in a more elegant way by keeping a private
      ticks_per_jiffy field in the delay ops, independent of loops_per_jiffy
      and therefore not subject to scaling. The loop-based delay continues to
      use loops_per_jiffy directly, as it should.
      Acked-by: NNicolas Pitre <nico@linaro.org>
      Signed-off-by: NWill Deacon <will.deacon@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6f3d90e5
    • C
      ARM: 7684/1: errata: Workaround for Cortex-A15 erratum 798181 (TLBI/DSB operations) · 93dc6887
      Catalin Marinas 提交于
      On Cortex-A15 (r0p0..r3p2) the TLBI/DSB are not adequately shooting down
      all use of the old entries. This patch implements the erratum workaround
      which consists of:
      
      1. Dummy TLBIMVAIS and DSB on the CPU doing the TLBI operation.
      2. Send IPI to the CPUs that are running the same mm (and ASID) as the
         one being invalidated (or all the online CPUs for global pages).
      3. CPU receiving the IPI executes a DMB and CLREX (part of the exception
         return code already).
      Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      93dc6887
    • R
      ARM: 7682/1: cache-l2x0: fix masking of RTL revision numbering and set_debug init · 6e7aceeb
      Rob Herring 提交于
      Commit b8db6b88 (ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache
      ctrl) moved the masking of the part ID which caused the RTL version to be
      lost. Commit 6248d060 (ARM: 7545/1: cache-l2x0: make outer_cache_fns a
      field of l2x0_of_data) changed how .set_debug is initialized. Both commits
      break commit 74ddcdb8 (ARM: 7608/1: l2x0: Only set .set_debug
      on PL310 r3p0 and earlier) which uses the RTL version to conditionally set
      .set_debug function pointer. Commit b8db6b88 also caused the printed cache
      ID to be missing the version information.
      
      Fix this by reverting how the part number is masked so the RTL version
      info is maintained. The cache-id-part DT property does not set the RTL
      bits so masking them should have no effect. Also, re-arrange the order
      of the function pointer init so the .set_debug function can be overridden.
      Reported-by: NPaolo Pisati <paolo.pisati@canonical.com>
      Signed-off-by: NRob Herring <rob.herring@calxeda.com>
      Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
      Cc: Yehuda Yitschak <yehuday@marvell.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      6e7aceeb
    • R
      ARM: iWMMXt: always enable iWMMXt support with PJ4 CPUs · 698613b6
      Russell King 提交于
      Jason Cooper reports these build errors:
      arch/arm/kernel/built-in.o: In function `iwmmxt_do':
      /.../arch/arm/kernel/pj4-cp0.c:36: undefined reference to `iwmmxt_task_release'
      /.../arch/arm/kernel/pj4-cp0.c:40: undefined reference to `iwmmxt_task_switch'
      make: *** [vmlinux] Error 1
      
      This is caused because the PJ4 code explicitly references the iWMMXt
      code, but doesn't require it to be built.  Fix this by ensuring that
      iWMMXt is always enabled with PJ4.
      Reported-by: NJason Cooper <jason@lakedaemon.net>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      698613b6
    • P
      x86: remove the x32 syscall bitmask from syscall_get_nr() · 8b4b9f27
      Paul Moore 提交于
      Commit fca460f9 simplified the x32
      implementation by creating a syscall bitmask, equal to 0x40000000, that
      could be applied to x32 syscalls such that the masked syscall number
      would be the same as a x86_64 syscall.  While that patch was a nice
      way to simplify the code, it went a bit too far by adding the mask to
      syscall_get_nr(); returning the masked syscall numbers can cause
      confusion with callers that expect syscall numbers matching the x32
      ABI, e.g. unmasked syscall numbers.
      
      This patch fixes this by simply removing the mask from syscall_get_nr()
      while preserving the other changes from the original commit.  While
      there are several syscall_get_nr() callers in the kernel, most simply
      check that the syscall number is greater than zero, in this case this
      patch will have no effect.  Of those remaining callers, they appear
      to be few, seccomp and ftrace, and from my testing of seccomp without
      this patch the original commit definitely breaks things; the seccomp
      filter does not correctly filter the syscalls due to the difference in
      syscall numbers in the BPF filter and the value from syscall_get_nr().
      Applying this patch restores the seccomp BPF filter functionality on
      x32.
      
      I've tested this patch with the seccomp BPF filters as well as ftrace
      and everything looks reasonable to me; needless to say general usage
      seemed fine as well.
      Signed-off-by: NPaul Moore <pmoore@redhat.com>
      Link: http://lkml.kernel.org/r/20130215172143.12549.10292.stgit@localhost
      Cc: <stable@vger.kernel.org>
      Cc: Will Drewry <wad@chromium.org>
      Cc: H. Peter Anvin <hpa@zytor.com>
      Signed-off-by: NH. Peter Anvin <hpa@linux.intel.com>
      8b4b9f27
  7. 02 4月, 2013 2 次提交
    • H
      s390/mm: provide emtpy check_pgt_cache() function · 765a0cac
      Heiko Carstens 提交于
      All architectures need to provide a check_pgt_cache() function. The s390 one
      got lost somewhere.
      So reintroduce it to prevent future compile errors e.g. if Thomas Gleixner's
      idle loop rework patches get merged.
      Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      765a0cac
    • H
      s390/uaccess: fix page table walk · ea81531d
      Heiko Carstens 提交于
      When translating user space addresses to kernel addresses the follow_table()
      function had two bugs:
      
      - PROT_NONE mappings could be read accessed via the kernel mapping. That is
        e.g. putting a filename into a user page, then protecting the page with
        PROT_NONE and afterwards issuing the "open" syscall with a pointer to
        the filename would incorrectly succeed.
      
      - when walking the page tables it used the pgd/pud/pmd/pte primitives which
        with dynamic page tables give no indication which real level of page tables
        is being walked (region2, region3, segment or page table). So in case of an
        exception the translation exception code passed to __handle_fault() is not
        necessarily correct.
        This is not really an issue since __handle_fault() doesn't evaluate the code.
        Only in case of e.g. a SIGBUS this code gets passed to user space. If user
        space can do something sane with the value is a different question though.
      
      To fix these issues don't use any Linux primitives. Only walk the page tables
      like the hardware would do it, however we leave quite some checks away since
      we know that we only have full size page tables and each index is within bounds.
      
      In theory this should fix all issues...
      Signed-off-by: NHeiko Carstens <heiko.carstens@de.ibm.com>
      Reviewed-by: NGerald Schaefer <gerald.schaefer@de.ibm.com>
      Signed-off-by: NMartin Schwidefsky <schwidefsky@de.ibm.com>
      ea81531d
  8. 31 3月, 2013 1 次提交
  9. 30 3月, 2013 2 次提交
  10. 29 3月, 2013 6 次提交
  11. 28 3月, 2013 4 次提交