1. 11 3月, 2016 1 次提交
    • A
      mtd: nand: Qualcomm NAND controller driver · c76b78d8
      Archit Taneja 提交于
      The Qualcomm NAND controller is found in SoCs like IPQ806x, MSM7xx,
      MDM9x15 series.
      
      It exists as a sub block inside the IPs EBI2 (External Bus Interface 2)
      and QPIC (Qualcomm Parallel Interface Controller). These IPs provide a
      broader interface for external slow peripheral devices such as LCD and
      NAND/NOR flash memory or SRAM like interfaces.
      
      We add support for the NAND controller found within EBI2. For the SoCs
      of our interest, we only use the NAND controller within EBI2. Therefore,
      it's safe for us to assume that the NAND controller is a standalone block
      within the SoC.
      
      The controller supports 512B, 2kB, 4kB and 8kB page 8-bit and 16-bit NAND
      flash devices. It contains a HW ECC block that supports BCH ECC (4, 8 and
      16 bit correction/step) and RS ECC(4 bit correction/step) that covers main
      and spare data. The controller contains an internal 512 byte page buffer
      to which we read/write via DMA. The EBI2 type NAND controller uses ADM DMA
      for register read/write and data transfers. The controller performs page
      reads and writes at a codeword/step level of 512 bytes. It can support up
      to 2 external chips of different configurations.
      
      The driver prepares register read and write configuration descriptors for
      each codeword, followed by data descriptors to read or write data from the
      controller's internal buffer. It uses a single ADM DMA channel that we get
      via dmaengine API. The controller requires 2 ADM CRCIs for command and
      data flow control. These are passed via DT.
      
      The ecc layout used by the controller is syndrome like, but we can't use
      the standard syndrome ecc ops because of several reasons. First, the amount
      of data bytes covered by ecc isn't same in each step. Second, writing to
      free oob space requires us writing to the entire step in which the oob
      lies. This forces us to create our own ecc ops.
      
      One more difference is how the controller accesses the bad block marker.
      The controller ignores reading the marker when ECC is enabled. ECC needs
      to be explicity disabled to read or write to the bad block marker. The
      nand_bbt helpers library hence can't access BBMs for the controller.
      For now, we skip the creation of BBT and populate chip->block_bad and
      chip->block_markbad helpers instead.
      Reviewed-by: NAndy Gross <agross@codeaurora.org>
      Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
      Signed-off-by: NArchit Taneja <architt@codeaurora.org>
      Reviewed-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      c76b78d8
  2. 02 2月, 2016 1 次提交
  3. 27 1月, 2016 1 次提交
  4. 08 1月, 2016 1 次提交
  5. 19 12月, 2015 1 次提交
  6. 10 12月, 2015 1 次提交
  7. 13 10月, 2015 1 次提交
  8. 30 9月, 2015 2 次提交
    • S
      mtd: nand: vf610_nfc: add hardware BCH-ECC support · 049f4250
      Stefan Agner 提交于
      This adds hardware ECC support using the BCH encoder in the NFC IP.
      The ECC encoder supports up to 32-bit correction by using 60 error
      correction bytes. There is no sub-page ECC step, ECC is calculated
      always across the whole page (up to 2k pages).
      
      Limitations:
      - HW ECC: Only 2K page with 64+ OOB.
      - HW ECC: Only 24 and 32-bit error correction implemented.
      
      Raw writes have been tested using the generic nand_write_page_raw
      implementation. However, raw reads are currently not possible
      because the controller need to know whether we are going to use
      the ECC mode already at NAND_CMD_READ0 command time. At this point
      we do not have the information whether it is a raw read or a
      regular read at driver level...
      Signed-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      049f4250
    • S
      mtd: nand: vf610_nfc: Freescale NFC for VF610, MPC5125 and others · 456930d8
      Stefan Agner 提交于
      This driver supports Freescale NFC (NAND flash controller) found on
      Vybrid (VF610), MPC5125, MCF54418 and Kinetis K70. The driver has
      been tested using 8-bit and 16-bit NAND interface on the ARM based
      Vybrid SoC VF500 and VF610 platform.
      parameter page reading.
      
      Limitations:
      - Untested on MPC5125 and M54418.
      - DMA and pipelining not used.
      - 2K pages or less.
      - No chip select, one NAND chip per controller.
      - No hardware ECC.
      
      Some paths have been hand-optimized and evaluated by measurements
      made using mtd_speedtest.ko on a 100MB MTD partition.
      
      Colibri VF50
              eb write     %   eb read     %   page write      %   page read     %
      rel/opt     5175           11537                4560             11039
      opt         5164 -0.21     11420 -1.01          4737 +3.88       10918 -1.10
      none        5113 -1.20     11352 -1.60          4490 -1.54       10865 -1.58
      
      Colibri VF61
              eb write     %   eb read     %   page write      %   page read     %
      rel/opt     5766           13096                5459             12846
      opt         5883 +2.03     13064 -0.24          5561 +1.87       12802 -0.34
      none        5701 -1.13     12980 -0.89          5488 +0.53       12735 -0.86
      
      rel = using readl_relaxed/writel_relaxed in optimized paths
      opt = hand-optimized by combining multiple accesses into one read/write
      
      The measurements have not been statistically verfied, hence use them
      with care. The author came to the conclusion that using the relaxed
      variants of readl/writel are not worth the additional code.
      Signed-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com>
      Tested-by: NAlbert ARIBAUD <albert.aribaud@3adev.fr>
      Signed-off-by: NStefan Agner <stefan@agner.ch>
      Reviewed-by: NAlexey Klimov <klimov.linux@gmail.com>
      Signed-off-by: NBrian Norris <computersforpeace@gmail.com>
      456930d8
  9. 19 8月, 2015 1 次提交
  10. 21 5月, 2015 1 次提交
  11. 16 5月, 2015 1 次提交
  12. 03 3月, 2015 1 次提交
  13. 08 2月, 2015 1 次提交
  14. 06 2月, 2015 1 次提交
  15. 05 11月, 2014 1 次提交
  16. 30 10月, 2014 1 次提交
  17. 07 10月, 2014 2 次提交
  18. 11 3月, 2014 1 次提交
  19. 01 3月, 2014 1 次提交
    • P
      powerpc: select MEMORY for FSL_IFC to not break existing .config files · 42d87b18
      Paul Gortmaker 提交于
      commit d2ae2e20 ("driver/memory:Move
      Freescale IFC driver to a common driver") introduces this build
      regression into the mpc85xx_defconfig:
      
       drivers/built-in.o: In function `fsl_ifc_nand_remove':
       drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/built-in.o: In function `fsl_ifc_nand_probe':
       drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/built-in.o: In function `match_bank':
       drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address'
       drivers/built-in.o: In function `fsl_ifc_nand_probe':
       drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev'
       drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev'
       make: *** [vmlinux] Error 1
      
      This happens because there is nothing to descend us into the
      drivers/memory directory in the mpc85xx_defconfig.  It wasn't
      selecting CONFIG_MEMORY.  So we never built drivers/memory/fsl_ifc.o
      and so we have nothing to link the above symbols against.
      
      Since the goal of the original commit was to relocate the driver to
      an arch independent location, it only makes sense to relocate the
      Kconfig setting there as well.  But that alone won't fix the build
      failure; for that we ensure whoever selects FSL_IFC also selects MEMORY.
      
      Cc: Prabhakar Kushwaha <prabhakar@freescale.com>
      Cc: Scott Wood <scottwood@freescale.com>
      Cc: Arnd Bergmann <arnd@arndb.de>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
      Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
      Signed-off-by: NGreg Kroah-Hartman <gregkh@linuxfoundation.org>
      42d87b18
  20. 04 1月, 2014 4 次提交
  21. 07 11月, 2013 1 次提交
  22. 31 8月, 2013 3 次提交
  23. 06 8月, 2013 1 次提交
  24. 19 6月, 2013 1 次提交
    • A
      mtd: omap2: allow bulding as a module · 930d800b
      Arnd Bergmann 提交于
      The omap2 nand device driver calls into the the elm code, which can
      be a loadable module, and in that case it cannot be built-in itself.
      I can see no reason why the omap2 driver cannot also be a module,
      so let's make the option "tristate" in Kconfig to fix this allmodconfig
      build error:
      
      ERROR: "elm_config" [drivers/mtd/nand/omap2.ko] undefined!
      ERROR: "elm_decode_bch_error_page" [drivers/mtd/nand/omap2.ko] undefined!
      Signed-off-by: NArnd Bergmann <arnd@arndb.de>
      Acked-by: NTony Lindgren <tony@atomide.com>
      Cc: David Woodhouse <dwmw2@infradead.org>
      Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
      Cc: Afzal Mohammed <afzal@ti.com>
      Cc: Russell King <rmk+kernel@arm.linux.org.uk>
      Cc: linux-mtd@lists.infradead.org
      930d800b
  25. 16 4月, 2013 1 次提交
  26. 05 4月, 2013 4 次提交
  27. 12 1月, 2013 1 次提交
  28. 10 12月, 2012 1 次提交
  29. 22 11月, 2012 2 次提交