Now the root gic_irq_domain is split into device and IPI domains.

This form provides a better representation of how the root domain is split into
2. One for devices and one for IPIs.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-14-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Add a new ipi domain on top of the normal domain.

MIPS GIC now supports dynamic allocation of an IPI.
Signed-off-by: NQais Yousef <qais.yousef@imgtec.com>
Acked-by: NRalf Baechle <ralf@linux-mips.org>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
Cc: <jiang.liu@linux.intel.com>
Cc: <linux-mips@linux-mips.org>
Cc: <lisa.parratt@imgtec.com>
Cc: Qais Yousef <qsyousef@gmail.com>
Link: http://lkml.kernel.org/r/1449580830-23652-13-git-send-email-qais.yousef@imgtec.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Moving an SPI around doesn't require any extra work from the rest
of the stack, and specially not for MSI-generated SPIs.

It is then worth returning IRQ_SET_MASK_OK_DONE instead of
IRQ_SET_MASK_OK, and simplify the other irqchips that rely on
this behaviour (GICv2m and Marvell's ODMI controller).
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Acked-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1455894029-17270-1-git-send-email-marc.zyngier@arm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commits adds a new irqchip driver that handles the ODMI
controller found on Marvell 7K/8K processors. The ODMI controller
provide MSI interrupt functionality to on-board peripherals, much like
the GIC-v2m.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1455888883-5127-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

ts4800_ic_ops is only referenced in this driver, so make it static.
In additional, it's never get modified thus also make it const.
Signed-off-by: NAxel Lin <axel.lin@ingics.com>
Reviewed-by: NDamien Riegel <damien.riegel@savoirfairelinux.com>
Link: https://lkml.kernel.org/r/1455457804.13175.1.camel@ingics.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The writel() immediately after this has a barrier, anyway.
Signed-off-by: NEric Anholt <eric@anholt.net>
Link: https://lkml.kernel.org/r/1454620468-31303-1-git-send-email-eric@anholt.netSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Technologic Systems TS-4800 is an i.MX515 board, so its drivers
are useless unless building a SOC_IMX51 kernel, except for build
testing purposes.
Signed-off-by: NJean Delvare <jdelvare@suse.de>
Cc: Damien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/20160209111920.1ec318bd@endymionSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This adds support for the secondary interrupt controller used in Sigma
Designs SMP86xx and SMP87xx chips.
Signed-off-by: NMans Rullgard <mans@mansr.com>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453313237-18570-2-git-send-email-mans@mansr.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453553867-27003-2-git-send-email-albeu@free.frSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The driver stays the same but the initialization changes a bit.
For OF boards we now get the memory map from the OF node and use
a linear mapping instead of the legacy mapping. For legacy boards
we still use a legacy mapping and just pass down all the parameters
from the board init code.
Signed-off-by: NAlban Bedel <albeu@free.fr>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1453553867-27003-1-git-send-email-albeu@free.frSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The irq-armada-370-xp driver can only be built for ARM 32 bits. The mvebu
family had grown with a new ARM64 SoC which will also select the
ARCH_MEVBU configuration. Since "ARM: mvebu: use the ARMADA_370_XP_IRQ
option", the ARM32 mvebu SoC directly select this new option. Selecting
it by default when ARCH_MEVBU is selected is no more needed.

This patch removes this dependency, thanks to this, a kernel for ARM64
mvebu SoC can be built without error due this driver.
Signed-off-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1454951660-13289-3-git-send-email-gregory.clement@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Add support for allocating multiple MSIs at the same time, so that the
MSI_FLAG_MULTI_PCI_MSI flag can be added to the msi_domain_info
structure.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-6-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

In order to make the output of /proc/interrupts, use shorter names for
the irq_chip registered by the irq-armada-370-xp driver. Using capital
letters also matches better what is done for the GIC driver, which
uses just "GIC" as the irq_chip->name.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-5-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

As suggested by Gregory Clement, this commit adjusts the
irq-armada-370-xp driver to use the PCI_MSI_DOORBELL_START define in
the armada_370_xp_handle_msi_irq() function, rather than hardcoding
its value.
Suggested-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

This commit moves the irq-armada-370-xp driver from using the
PCI-specific MSI infrastructure to the generic MSI infrastructure, to
which drivers are progressively converted.

In this hardware, the MSI controller is directly bundled inside the
interrupt controller, so we have a single Device Tree node to which
multiple IRQ domaines are attached: the wired interrupt domain and the
MSI interrupt domain. In order to ensure that they can be
differentiated, we have to force the bus_token of the wired interrupt
domain to be DOMAIN_BUS_WIRED. The MSI domain bus_token is
automatically set to the appropriate value by
pci_msi_create_irq_domain().
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Suggested-by: NMarc Zyngier <marc.zyngier@arm.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Link: https://lkml.kernel.org/r/1455115621-22846-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Instead of building the irq-armada-370-xp driver directly when
CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate
CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option.

This allows this option to select other interrupt-related Kconfig
options (which will be needed in follow-up commits) rather than having
such selects done from arch/arm/mach-<foo>/.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1455115621-22846-2-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Add the BCM6345 interrupt controller based on the SMP-capable BCM7038
and the BCM3380 but with packed interrupt registers.

Add the BCM6345 interrupt controller to a list with the existing BCM7038
so that interrupts on CPU1 are not ignored.

Update the maintainers file list for BMIPS to include this driver.
Signed-off-by: NSimon Arlott <simon@fire.lp0.eu>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: linux-mips@linux-mips.org
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Rob Herring <robh@kernel.org>
Link: http://lkml.kernel.org/r/5651D176.6030908@simon.arlott.org.ukSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

AIC5 priority value is updated twice -
in aic_common_set_priority() and when updating AT91_AIC5_SMR.
Variable, 'smr' has updated priority value (intspec[2]) in the first step,
so no need to update it again in the second step.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Cc: Nicholas Ferre <nicolas.ferre@atmel.com>
Link: http://lkml.kernel.org/r/1452669592-3401-4-git-send-email-milo.kim@ti.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Priority validation is not necessary because aic_common_irq_domain_xlate()
already handles it. With this removal, return type can be changed to void.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Cc: Nicholas Ferre <nicolas.ferre@atmel.com>
Link: http://lkml.kernel.org/r/1452669592-3401-3-git-send-email-milo.kim@ti.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

AIC IRQ fixup is handled in each IRQ chip driver.
It can be moved into aic_common_of_init() before returning the result.
Then, aic_common_irq_fixup() can be changed to static type.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Cc: Nicholas Ferre <nicolas.ferre@atmel.com>
Link: http://lkml.kernel.org/r/1452669592-3401-1-git-send-email-milo.kim@ti.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The rework of the driver missed to move the call to set_handle_irq() into
asm9260_of_init(). As a consequence no interrupt entry point is installed and
no interrupts are delivered

Solution is simple: Install the interrupt entry handler.

Fixes: 7e4ac676 ("irqchip/mxs: Add Alphascale ASM9260 support")
Signed-off-by: NOleksij Rempel <linux@rempel-privat.de>
Cc: kernel@pengutronix.de
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: stable@vger.kernel.org
Link: http://lkml.kernel.org/r/1454061473-24957-1-git-send-email-linux@rempel-privat.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Atmel AIC has common structure for SMR (Source Mode Register).

  bit[6:5] Interrupt source type
  bit[2:0] Priority level
  Other bits are unused.

To update new priority value, bit[2:0] should be cleared first and then
new priority level can be written. However, aic_common_set_priority()
helper clears source type bits instead of priority bits.
This patch fixes wrong mask bit operation.

Fixes: b1479ebb "irqchip: atmel-aic: Add atmel AIC/AIC5 drivers"
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Acked-by: NBoris Brezillon <boris.brezillon@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Ludovic Desroches <ludovic.desroches@atmel.com>
Cc: Nicholas Ferre <nicolas.ferre@atmel.com>
Cc: stable@vger.kernel.org #v3.17+
Link: http://lkml.kernel.org/r/1452669592-3401-2-git-send-email-milo.kim@ti.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

When the programming of a GITS_BASERn register fails because of
an unsupported ITS page size, we retry it with a smaller page size.
Unfortunately, we don't recompute the number of allocated ITS pages,
indicating the wrong value computed in the original allocation.

A convenient fix is to free the pages we allocated, update the
page size, and restart the allocation. This will ensure that
we always allocate the right amount in the case of a device
table, specially if we have to reduce the allocation order
to stay within the boundaries of the ITS maximum allocation.
Reported-and-tested-by: NMa Jun <majun258@huawei.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1453818255-1289-1-git-send-email-marc.zyngier@arm.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Not every arch has io memory. So, unbreak the build by fixing the
dependencies.
Signed-off-by: NRichard Weinberger <richard@nod.at>
Cc: user-mode-linux-devel@lists.sourceforge.net
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Link: http://lkml.kernel.org/r/1453760661-1444-19-git-send-email-richard@nod.atSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The init_eint array in the s3c24xx irqchip driver is used by
every individual chip variant, but Kconfig allows building
the driver when they are all disabled, and that leads to
a harmless compile-time warning:

drivers/irqchip/irq-s3c24xx.c:608:28: error: 'init_eint' defined but not used [-Werror=unused-variable]

This marks the array as __maybe_unused to avoid the warning.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jason Cooper <jason@lakedaemon.net>
Link: http://lkml.kernel.org/r/1453737499-1960073-1-git-send-email-arnd@arndb.deSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This adds support for the interrupt controller present on PIC32 class
devices. It handles all internal and external interrupts. This controller
exists outside of the CPU core and is the arbitrator of all interrupts
(including interrupts from the CPU itself) before they are presented to
the CPU.

The following features are supported:
 - DT properties for EVIC and for devices/peripherals that use interrupt lines
 - Persistent and non-persistent interrupt handling
 - irqdomain and generic chip support
 - Configuration of external interrupt edge polarity
Signed-off-by: NCristian Birsan <cristian.birsan@microchip.com>
Signed-off-by: NJoshua Henderson <joshua.henderson@microchip.com>
Acked-by: NThomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/12092/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

Commit 13ae42a3b1c1 ("h8300: Rename ctlr_out/in[bwl] to
raw_read/write[bwl]") changed the function names, but not all callers,
resulting in

drivers/irqchip/irq-renesas-h8s.c: In function ‘h8s_disable_irq’:
drivers/irqchip/irq-renesas-h8s.c:43:9: error:
	implicit declaration of function ‘ctrl_inw’
drivers/irqchip/irq-renesas-h8s.c:44:2: error:
	implicit declaration of function ‘ctrl_outw’

Fixes: 13ae42a3b1c1 ("h8300: Rename ctlr_out/in[bwl] to raw_read/write[bwl]")
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: NGuenter Roeck <linux@roeck-us.net>

Under some conditions, irq sorting procedure used by INTC can go wrong
resulting in a spurious irq getting reported.

If this condition is not handled, it results in endless stream of:

    unexpected IRQ trap at vector 00

messages from ack_bad_irq()

Handle the spurious interrupt condition in omap-intc driver to prevent this.

Measurements using kernel function profiler on AM335x EVM running at 720MHz
show that after this patch omap_intc_handle_irq() takes about 37.4us against
34us before this patch.
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Acked-by: NTony Lindgren <tony@atomide.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Link: http://lkml.kernel.org/r/9c78a6db02ac55f7af7371b417b6e414d2c3095b.1450188128.git.nsekhar@ti.com
Cc: stable@vger.kernel.org
Signed-off-by: NThomas Gleixner <tglx@linutronix.de>

Use irq_data_get_chip_type() instead of container_of().
Signed-off-by: NGeliang Tang <geliangtang@163.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Link: http://lkml.kernel.org/r/4cc3a3a7a74c7a1894892a85aa7eabbd1534fe96.1451484758.git.geliangtang@163.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Some OMAP interrupt controllers use generic level detection, so
handle_level_irq() is used as the chip type handler.
Allocated IRQ chip type handler doesn't need to set it again because
irq_alloc_domain_generic_chips() has already registered it.

Tested with BeagleBoneBlack Rev C.
Signed-off-by: NMilo Kim <milo.kim@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-omap@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Link: http://lkml.kernel.org/r/1450687994-12580-1-git-send-email-milo.kim@ti.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This commit adds support for the TS-4800 interrupt controller. This
controller is instantiated in a companion FPGA, and multiplex interrupts
for other FPGA IPs.

As this component is external to the SoC, the SoC might need to reserve
pins, so this controller is implemented as a platform driver and doesn't
use the IRQCHIP_DECLARE construct.
Signed-off-by: NDamien Riegel <damien.riegel@savoirfairelinux.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: kernel@savoirfairelinux.com
Link: http://lkml.kernel.org/r/1450728683-31416-2-git-send-email-damien.riegel@savoirfairelinux.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This patch contain fixes for v2m resources and SPI ranges:

  * Fix off-by-one error when set up v2m resource end range in
    gicv2m_acpi_init().

  * Fix the off-by-one print error for SPI range.

  * Use %pR to properly print resource range information.

Both ACPI and DT should now print:

  GICv2m: range[mem 0xe1180000-0xe1180fff], SPI[64:319]
Suggested-by: NBjorn Helgaas <bhelgaas@google.com>
Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <Catalin.Marinas@arm.com>
Cc: <hanjun.guo@linaro.org>
Cc: <tomasz.nowicki@linaro.org>
Cc: <graeme.gregory@linaro.org>
Cc: <dhdang@apm.com>
Cc: <linux-arm-kernel@lists.infradead.org>
Cc: <marc.zyngier@arm.com>
Cc: <jason@lakedaemon.net>
Cc: <rjw@rjwysocki.net>
Link: http://lkml.kernel.org/r/1450830263-28914-1-git-send-email-Suravee.Suthikulpanit@amd.comSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

Avoid using hardcoded magics. We have a #define for this number.
No functional changes.
Signed-off-by: NAndrea Merello <andrea.merello@gmail.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NEric Anholt <eric@anholt.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-5-git-send-email-eric@anholt.netSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

On my RPi2 I got a lot of:
unexpected IRQ trap at vector 00

This happens because bcm2836_arm_irqchip_handle_irq() is sometimes
invoked even if the ISR is clear, and this case is not handled.

This patch explicitly handle this case, fixing the kernel complaints
about the bad IRQ lookup.
Signed-off-by: NAndrea Merello <andrea.merello@gmail.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NEric Anholt <eric@anholt.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-4-git-send-email-eric@anholt.netSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The firmware sets the secondaries spinning waiting for a non-NULL
value to show up in the last IPI mailbox.

The original SMP port from the downstream tree was done by Andrea, and
Eric cleaned it up/rewrote it a few times from there.
Signed-off-by: NAndrea Merello <andrea.merello@gmail.com>
Signed-off-by: NEric Anholt <eric@anholt.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-3-git-send-email-eric@anholt.netSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

The irqchip's register area includes the the setup for the timer's
scaling factors, and for the platform we want a fixed configuration of
these registers.
Signed-off-by: NEric Anholt <eric@anholt.net>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Lee Jones <lee@kernel.org>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: linux-rpi-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1451166444-11044-2-git-send-email-eric@anholt.netSigned-off-by: NThomas Gleixner <tglx@linutronix.de>

This patch introduces gicv2m_acpi_init(), which uses information
in MADT GIC MSI frames structure to initialize GICv2m driver.
It also exposes gicv2m_init() function, which simplifies callers
to a single GICv2m init function.
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Tested-by: NDuc Dang <dhdang@apm.com>
Acked-by: NRafael J. Wysocki <rjw@rjwysocki.net>
Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: NHanjun Guo <hanjun.guo@linaro.org>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

This patch replaces the struct device_node with struct fwnode_handle
since this structure is common between DT and ACPI.

It also refactors gicv2m_init_one() to prepare for ACPI support.
The only functional change is removing the node name from pr_info.
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Since there will be several places checking if fwnode.type
is equal FWNODE_IRQCHIP, this patch adds a convenient function
for this purpose.
Acked-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>

Add the interrupt controller chip operation functions of mbigen chip.
Signed-off-by: NMa Jun <majun258@huawei.com>
Reviewed-by: NMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>